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41110
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Intel® 41110 Serial to Parallel PCI Bridge Design Guide
Power Plane Layout
Figure 8.
Decoupling Placement for PCI/PCI-X 1
.5V and 3.3V Voltage Planes
B2714-01
Capacitor Legend
0603-0.1 F
0603-1 F
1206-10 F
Contents
Main
ii Intel 41110 Serial to Parallel PCI Bridge Design Guide
Contents
Figures
Tables
Page
Page
About This Document 1
1.1 Terminology and Definitions
About This Document
Table 1. Terminology and Definitions (Sheet 2 of 2)
Introduction 2
2.1 PCI Express Interface Features
2.2 PCI-X Interface Features
2.3 Power Management
2.4 SMBus Interface
2.4.1 SMBus for configuration register initialization
Page
2.5 JTAG
2.6 Related Documents
Page
Page
Package Information 3
3.1 Package Specification
Package Information Figure 6. 41110 Bridge Package Dimensions (Side View)
Power Plane Layout 4
4.1 41110 Decoupling Guidelines
Page
Power Plane Layout Table 2. 41110 Decoupling Guidelines
4.2 Split Voltage Planes
There are two 1.5V voltage planes that supply power to the 41110:
Page
41110 Reset and Power Timing Considerations 5
5.1 A_RST# and PERST# Timing Requirements
5.2 VCC15 and VCC33 Voltage Requirements
Page
General Routing Guidelines 6
6.1 General Routing Guidelines
6.2 Crosstalk
6.3 EMI Considerations
6.4 Power Distribution and Decoupling
6.4.1 Decoupling
6.5 Trace Impedance
6.5.1 Differential Impedance
Z
Z11 Z12 Z21 Z22
=
Board Layout Guidelines 7
7.1 Adapter Card Topology
Page
PCI-X Layout Guidelines 8
8.1 Interrupts
8.1.1 Interrupt Routing for Devices Behind a Bridge
8.2 PCI Arbitration
8.2.1 PCI Resistor Compensation
8.3 PCI General Layout Guidelines
8.3.1 PCI Pullup Resistors Not Required
8.4 PCI Clock Layout Guidelines
Page
Table 8. PCI-X Clock Layout Requirements Summary
8.5 PCI-X Topology Layout Guidelines
8.6 41110 Layout Analysis
8.6.1 Embedded PCI-X 133 MHz
8.6.2 Embedded PCI-X 100 MHz
Table 11. Embedded PCI-X 100 MHz Routing Recommendations
8.6.3 PCI-X 66 MHz Embedded Topology
Table 12. PCI-X 66 MHz Embedded Routing Recommendations
8.6.4 PCI 66 MHz Embedded Topology
Figure 20 and Tabl e 13 provide routing details for a topology with an embedded PCI 66MHz design.
Figure 20. PCI 66 MHz Embedded Topology
Table 13. PCI 66 MHz Embedded Table
8.6.5 PCI 33 MHz Embedded Mode Topology
Table 14. PCI 33 MHz Embedded Routing Recommendations
PCI Express Layout 9
9.1 General recommendations
9.2 PCI-Express Layout Guidelines
9.3 Adapter Card Layout Guidelines
Page
Page
Circuit Implementations 10
10.1 41110 Analog Voltage Filters
10.1.1 PCI Analog Voltage Filters
10.1.2 PCI Express Analog Voltage Filter
10.1.3 Bandgap Analog Voltage Filter
10.2 41110 Reference and Compensation Pins
10.2.1 SM Bus
Page
41110 Customer Reference Boards 11
11.1 Board Stack-up
11.2 Materi al
11.3 Impedance
Page
Page
Design Guide Checklist 12
Table 20. PCI/PCI-X Interface S ignals (Sheet 1 of 2)
Table 21. Miscellaneous Signals
Table 20. PCI/PCI-X I nterface Signals (Sheet 2 of 2)
Table 22. SMB us Interface Signals
Table 21. Miscellaneous Signals
Table 23. Reset Pins
Table 24. Power and Ground Signals
