Pci | Intel 41110 manual

Power Plane Layout

Note: Linear voltage regulators are recommended when using 1.5 Volt power supplies.

Figure 9. 41110 Bridge Single-Layer Split Voltage Plane

Core

PCI

Express

B2715-01

20	Intel® 41110 Serial to Parallel PCI Bridge Design Guide

Image 20

Intel 41110 manual Pci

Contents

Intel 41110 Serial to Parallel PCI Bridge Design Guide Intel 41110 Serial to Parallel PCI Bridge Design Guide Contents Figures Tables Contents Revision History Date Revision Description March 001 Initial release About This Document Terminology and DefinitionsTerminology and Definitions Sheet 1 Term Definition About This Document Terminology and Definitions Sheet 2 Introduction2 PCI Express Interface FeaturesPCI-X Interface Features Power Management SMBus for configuration register initializationSMBus Interface Introduction Microcontroller Block Diagram Microcontroller Connections to Jtag Related Documents Block Diagram Intel 41110 Serial to Parallel PCI Bridge Applications Adapter Card Block Diagram Package Specification Package Information Bridge Package Dimensions Side View Package Information Power Plane Layout 41110 Decoupling Guidelines Power Plane Layout Split Voltage Planes Decoupling Guidelines41110 300 PCI VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations5ARST# and PERST# Timing Requirements Reset and Power Timing Considerations Crosstalk General Routing GuidelinesGeneral Routing Guidelines EMI Considerations General Routing Guidelines Decoupling Power Distribution and DecouplingTrace Impedance Differential Impedance Cross Section of Differential Trace Adapter Card Stack Up, Microstrip and Stripline Board Layout GuidelinesAdapter Card Topology Board Layout Guidelines Adapter Card Stackup AINT# Interrupt Pins PCI Express INTx Message PCI-X Layout GuidelinesInterrupts INTx Routing Table PCI Arbitration Interrupt Routing for Devices Behind a BridgePCI-X Layout Guidelines Interrupt Binding for Devices Behind a Bridge PCI General Layout Guidelines PCI Resistor Compensation PCI-X Signals PCI Clock Layout GuidelinesPCI Pullup Resistors Not Required PCI/PCI-X Frequency/Mode Straps PCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing Guidelines PCI-X Slot Guidelines PCI-X Topology Layout Guidelines41110 Layout Analysis Parameter Routing Guideline for Lower AD Bus Embedded PCI-X 133 MHzEmbedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing Recommendations PCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing Recommendations PCI 66 MHz Embedded Topology PCI 66 MHz Embedded Table PCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing Recommendations PCI Express Layout General recommendations PCI-Express Layout Guidelines Adapter Card Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1 Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Config Circuit Implementations10.1 41110 Analog Voltage Filters Circuit Implementations PCI Analog Voltage Filters PCI Express Analog Voltage Filter Bandgap Analog Voltage Filter PCI Express Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation Pins Bandgap Analog Voltage Filter Circuit Bit Value SMBUs Address ConfigurationSM Bus This page intentionally left blank Layer Type Thickness Copper Weight Customer Reference BoardsBoard Stack-up CRB Board Stackup Sheet 1 Material ImpedanceCustomer Reference Boards CRB Board Stackup Sheet 2 Board Outline Mechanical Outline This page intentionally left blank Design Guide Checklist PCI Express Interface SignalsSignals Recommendations Reason/Impact PERCOMP10 Design Guide Checklist PCI/PCI-X Interface Signals Sheet 1 PCI/PCI-X Interface Signals Sheet 2 Miscellaneous Signals SMBus Interface Signals Recommendations Reason/Impact Reset Pins Ballout Pin Name Usage Power and Ground Signals Signal Recommendations Reason/Impact Jtag Signals This page intentionally left blank