Embedded PCI-X 133 MHz | Intel 41110 instruction

PCI-X Layout Guidelines

8.6.1Embedded PCI-X 133 MHz

This section lists the routing recommendations for PCI-X 133 MHz without a slot. Figure 17 shows the block diagram of this topology and Table 10 describes the routing recommendations.

Figure 17. Embedded PCI-X 133 MHz Topology

		EM1
		TL EM1
		TL1
		TL EM2
		EM2
			B2719 -01

Table 10.	Embedded PCI-X 133 MHz Routing Recommendations

	Parameter	Routing Guideline for Lower AD Bus

	Reference Plane	Route over an unbroken ground plane

	Board Impedance	60 Ω +/- 15%

	Stripline Trace Spacing	12 mils from edge to edge

	Microstrip Trace Spacing	18 mils, from edge to edge

	Break Out	5 mils on 5 mils spacing. Maximum length of breakout region can be 500 mils

	Group Spacing	Spacing from other groups: 25 mils min, edge to edge

	Trace Length 1 (TL1): From
	41110 signal Ball to first	1.75” min - 4.0” max
	junction

	Trace Length 3 junction of
	TL_EM1 and TL_EM2 to the	1.25” min - 3.25” max
	embedded device
	Length Matching	Clocks coming form the clock driver must be on the same layer and length
	Requirements:	matched to within 25 mils.

	Number of vias	3 vias max per path

36	Intel® 41110 Serial to Parallel PCI Bridge Design Guide

Image 36

Intel 41110 manual Embedded PCI-X 133 MHz Routing Recommendations, Parameter Routing Guideline for Lower AD Bus

Contents

Intel 41110 Serial to Parallel PCI Bridge Design Guide Intel 41110 Serial to Parallel PCI Bridge Design Guide Contents Figures Tables Contents Revision History Date Revision Description March 001 Initial release About This Document Terminology and DefinitionsTerminology and Definitions Sheet 1 Term Definition About This Document Terminology and Definitions Sheet 2 PCI Express Interface Features PCI-X Interface FeaturesIntroduction2 Power Management SMBus for configuration register initializationSMBus Interface Introduction Microcontroller Block Diagram Microcontroller Connections to Jtag Related Documents Block Diagram Intel 41110 Serial to Parallel PCI Bridge Applications Adapter Card Block Diagram Package Specification Package Information Bridge Package Dimensions Side View Package Information Power Plane Layout 41110 Decoupling Guidelines Power Plane Layout Split Voltage Planes Decoupling Guidelines41110 300 PCI Reset and Power Timing Considerations5 ARST# and PERST# Timing RequirementsVCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk EMI Considerations General Routing Guidelines Power Distribution and Decoupling Trace ImpedanceDecoupling Differential Impedance Cross Section of Differential Trace Board Layout Guidelines Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Adapter Card Stackup AINT# Interrupt Pins PCI Express INTx Message PCI-X Layout GuidelinesInterrupts INTx Routing Table PCI Arbitration Interrupt Routing for Devices Behind a BridgePCI-X Layout Guidelines Interrupt Binding for Devices Behind a Bridge PCI General Layout Guidelines PCI Resistor Compensation PCI-X Signals PCI Clock Layout GuidelinesPCI Pullup Resistors Not Required PCI/PCI-X Frequency/Mode Straps PCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing Guidelines PCI-X Topology Layout Guidelines 41110 Layout AnalysisPCI-X Slot Guidelines Embedded PCI-X 133 MHz Embedded PCI-X 133 MHz Routing RecommendationsParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing Recommendations PCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing Recommendations PCI 66 MHz Embedded Topology PCI 66 MHz Embedded Table PCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing Recommendations PCI Express Layout General recommendations PCI-Express Layout Guidelines Adapter Card Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1 Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Config Circuit Implementations10.1 41110 Analog Voltage Filters Circuit Implementations PCI Analog Voltage Filters PCI Express Analog Voltage Filter Bandgap Analog Voltage Filter PCI Express Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation Pins Bandgap Analog Voltage Filter Circuit SMBUs Address Configuration SM BusBit Value This page intentionally left blank Layer Type Thickness Copper Weight Customer Reference BoardsBoard Stack-up CRB Board Stackup Sheet 1 Material ImpedanceCustomer Reference Boards CRB Board Stackup Sheet 2 Board Outline Mechanical Outline This page intentionally left blank Design Guide Checklist PCI Express Interface SignalsSignals Recommendations Reason/Impact PERCOMP10 Design Guide Checklist PCI/PCI-X Interface Signals Sheet 1 PCI/PCI-X Interface Signals Sheet 2 Miscellaneous Signals SMBus Interface Signals Recommendations Reason/Impact Reset Pins Ballout Pin Name Usage Power and Ground Signals Signal Recommendations Reason/Impact Jtag Signals This page intentionally left blank