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41110 Customer Reference Boards

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54	Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Intel 41110 manual This page intentionally left blank

Contents

Intel 41110 Serial to Parallel PCI Bridge Design Guide Intel 41110 Serial to Parallel PCI Bridge Design Guide Contents Figures Tables Contents Revision History Date Revision Description March 001 Initial release Terminology and Definitions Sheet 1 About This DocumentTerminology and Definitions Term Definition About This Document Terminology and Definitions Sheet 2 PCI Express Interface Features PCI-X Interface FeaturesIntroduction2 SMBus Interface Power ManagementSMBus for configuration register initialization Introduction Microcontroller Block Diagram Microcontroller Connections to Jtag Related Documents Block Diagram Intel 41110 Serial to Parallel PCI Bridge Applications Adapter Card Block Diagram Package Specification Package Information Bridge Package Dimensions Side View Package Information Power Plane Layout 41110 Decoupling Guidelines Power Plane Layout 41110 Split Voltage PlanesDecoupling Guidelines 300 PCI Reset and Power Timing Considerations5 ARST# and PERST# Timing RequirementsVCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk EMI Considerations General Routing Guidelines Power Distribution and Decoupling Trace ImpedanceDecoupling Differential Impedance Cross Section of Differential Trace Board Layout Guidelines Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Adapter Card Stackup Interrupts AINT# Interrupt Pins PCI Express INTx MessagePCI-X Layout Guidelines INTx Routing Table PCI-X Layout Guidelines PCI ArbitrationInterrupt Routing for Devices Behind a Bridge Interrupt Binding for Devices Behind a Bridge PCI General Layout Guidelines PCI Resistor Compensation PCI Pullup Resistors Not Required PCI-X SignalsPCI Clock Layout Guidelines PCI/PCI-X Frequency/Mode Straps PCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing Guidelines PCI-X Topology Layout Guidelines 41110 Layout AnalysisPCI-X Slot Guidelines Embedded PCI-X 133 MHz Embedded PCI-X 133 MHz Routing RecommendationsParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing Recommendations PCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing Recommendations PCI 66 MHz Embedded Topology PCI 66 MHz Embedded Table PCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing Recommendations PCI Express Layout General recommendations PCI Express Layout PCI-Express Layout GuidelinesAdapter Card Layout Guidelines Adapter Card Routing Recommendations Sheet 1 Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank 10.1 41110 Analog Voltage Filters ConfigCircuit Implementations Circuit Implementations PCI Analog Voltage Filters PCI Express Analog Voltage Filter Bandgap Analog Voltage Filter PCI Express Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation Pins Bandgap Analog Voltage Filter Circuit SMBUs Address Configuration SM BusBit Value This page intentionally left blank Board Stack-up Layer Type Thickness Copper WeightCustomer Reference Boards CRB Board Stackup Sheet 1 Customer Reference Boards MaterialImpedance CRB Board Stackup Sheet 2 Board Outline Mechanical Outline This page intentionally left blank Signals Recommendations Reason/Impact Design Guide ChecklistPCI Express Interface Signals PERCOMP10 Design Guide Checklist PCI/PCI-X Interface Signals Sheet 1 PCI/PCI-X Interface Signals Sheet 2 Miscellaneous Signals SMBus Interface Signals Recommendations Reason/Impact Reset Pins Ballout Pin Name Usage Power and Ground Signals Signal Recommendations Reason/Impact Jtag Signals This page intentionally left blank