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Reset and Power Timing Considerations
Models:
41110
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Specs
Microcontroller Block Diagram
PCI-X Signals
Config
Reset Pins
Checklist
Power Management
PCI Express Interface Features
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41110 Reset and Power Timing Considerations
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IntelĀ® 41110 Serial to Parallel PCI Bridge Design Guide
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Contents
Intel 41110 Serial to Parallel PCI Bridge
Design Guide
Intel 41110 Serial to Parallel PCI Bridge Design Guide
Contents
Figures
Tables
Contents
Revision History
Date Revision Description March 001 Initial release
Terminology and Definitions Sheet 1
About This Document
Terminology and Definitions
Term Definition
About This Document
Terminology and Definitions Sheet 2
PCI-X Interface Features
PCI Express Interface Features
Introduction2
SMBus Interface
Power Management
SMBus for configuration register initialization
Introduction
Microcontroller Block Diagram
Microcontroller Connections to
Jtag
Related Documents
Block Diagram
Intel 41110 Serial to Parallel PCI Bridge Applications
Adapter Card Block Diagram
Package Specification
Package Information
Bridge Package Dimensions Side View
Package Information
Power Plane Layout
41110 Decoupling Guidelines
Power Plane Layout
41110
Split Voltage Planes
Decoupling Guidelines
300
PCI
ARST# and PERST# Timing Requirements
Reset and Power Timing Considerations5
VCC15 and VCC33 Voltage Requirements
Reset and Power Timing Considerations
General Routing Guidelines
General Routing Guidelines
Crosstalk
EMI Considerations
General Routing Guidelines
Trace Impedance
Power Distribution and Decoupling
Decoupling
Differential Impedance
Cross Section of Differential Trace
Adapter Card Topology
Board Layout Guidelines
Adapter Card Stack Up, Microstrip and Stripline
Board Layout Guidelines
Adapter Card Stackup
Interrupts
AINT# Interrupt Pins PCI Express INTx Message
PCI-X Layout Guidelines
INTx Routing Table
PCI-X Layout Guidelines
PCI Arbitration
Interrupt Routing for Devices Behind a Bridge
Interrupt Binding for Devices Behind a Bridge
PCI General Layout Guidelines
PCI Resistor Compensation
PCI Pullup Resistors Not Required
PCI-X Signals
PCI Clock Layout Guidelines
PCI/PCI-X Frequency/Mode Straps
PCI Clock Distribution and Matching Requirements
PCI-X Clock Layout Requirements Summary
Parameter Routing Guidelines
41110 Layout Analysis
PCI-X Topology Layout Guidelines
PCI-X Slot Guidelines
Embedded PCI-X 133 MHz Routing Recommendations
Embedded PCI-X 133 MHz
Parameter Routing Guideline for Lower AD Bus
Embedded PCI-X 100 MHz
Embedded PCI-X 100 MHz Routing Recommendations
PCI-X 66 MHz Embedded Topology
PCI-X 66 MHz Embedded Routing Recommendations
PCI 66 MHz Embedded Topology
PCI 66 MHz Embedded Table
PCI 33 MHz Embedded Mode Topology
PCI 33 MHz Embedded Routing Recommendations
PCI Express Layout
General recommendations
PCI Express Layout
PCI-Express Layout Guidelines
Adapter Card Layout Guidelines
Adapter Card Routing Recommendations Sheet 1
Adapter Card Routing Recommendations Sheet 2
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10.1 41110 Analog Voltage Filters
Config
Circuit Implementations
Circuit Implementations
PCI Analog Voltage Filters
PCI Express Analog Voltage Filter
Bandgap Analog Voltage Filter
PCI Express Analog Voltage Filter Circuit
10.2 41110 Reference and Compensation Pins
Bandgap Analog Voltage Filter Circuit
SM Bus
SMBUs Address Configuration
Bit Value
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Board Stack-up
Layer Type Thickness Copper Weight
Customer Reference Boards
CRB Board Stackup Sheet 1
Customer Reference Boards
Material
Impedance
CRB Board Stackup Sheet 2
Board Outline
Mechanical Outline
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Signals Recommendations Reason/Impact
Design Guide Checklist
PCI Express Interface Signals
PERCOMP10
Design Guide Checklist
PCI/PCI-X Interface Signals Sheet 1
PCI/PCI-X Interface Signals Sheet 2
Miscellaneous Signals
SMBus Interface Signals
Recommendations Reason/Impact
Reset Pins
Ballout Pin Name Usage
Power and Ground Signals
Signal Recommendations Reason/Impact
Jtag Signals
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