Intel IXP400 8.10 Restrictions of the DMA Transfer

Intel® IXP400 Software
Access-Layer Components: DMA Access Driver (IxDmaAcc) API
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007 127
8. The descriptor pool needs to be guarded by mutual exclusion because there are two contexts
that access the pool descriptor buffer (see Step 3).
9. IxDmaAccCallback frees the descriptor.
The descriptor pool needs to be guarded by mutual exclusion (see Step 3).
10. IxDmaAccCallback calls client registered callback.
11. Client releases the resources allocated in Step 0.
8.10 Restrictions of the DMA Transfer
The client is responsible for ensuring that the following restrictions are followed when issuing a
DMA request:
•The Intel XScale core is operating in the big-endian mode.
•The host devices are operating in big-endian mode. This means that the valid bytes for 8-bit
and 16-bit transfer width are in the most-significant bytes (MSB). For example, for the 16-bit
transfer, the data is 0xAABBXXXX, where X is don’t care value.
— There is a slight difference in the access to the APB memory map region, specifically for
UART accessed. A read from an APB target is a 32-bit read from a word-aligned address.
— In the case of the UART Rx and Tx FIFOs, only the least significant byte (bits 7:0) of each
word read/written contains valid data not in the MSB. Therefore, instead of using
0xC8000000 for UART1 and 0xC8001000 for UART2, any DMA request involving the
UARTs must instead specify an address of 0xC8000003 for UART1 and 0xC8001003 for
UART2 (in both cases the transfer width should be set to 8 bits). APB discards 1:0 bit
address when decoding the AHB addresses. Therefore, valid data is read in MSB.
•Fixed address does not support burst mode. Fixed address associates with a single transaction.
This means that the fixed address will either have a transfer width of 8-bit, 16-bit, or 32-bit
single transaction. Fixed address (either fixed source address or fixed destination address) does
not support burst transaction because burst transaction will always increment the address
throughout the transaction. In addition, the AHB coprocessor does not have an instruction set
to do burst transfer on fixed address mode.
•Fixed source address with copy and clear transfer mode, the source is clear only once after the
transfer is completed.
•In the fixed source address mode, the client application is responsible to ensure that the data is
available for transfer. For example, using FIFO with entry size 32-bit as a fixed address mode
with the transfer length of 8 bytes, the client must ensure that the data is available before the
DMA transfer is performed.
•Due to the asymmetric nature of the expansion bus, the incrementing source address and a
“burst” transfer width will not support the “copy and clear” mode for expansion bus sources.
The reason that this mode is not supported is that expansion bus targets can be read in burst
mode, but they cannot be written in burst mode.
•If DMA transfer mode of “Byte-Swapped” or “Byte Reverse” is selected and if the Source
DMA Addressing mode is “Incremental,” the DMA Source address must be “word-aligned”
and the DMA transfer length would be a multiple of words. The reason is that endianness
swapping will always be done on the word boundary.