Intel IXP400 manual Access-Layer Components Parity Error Notifier IxParityENAcc, Introduction

Intel® IXP400 Software

Access-Layer Components:
Parity Error Notifier (IxParityENAcc)	16
API

This chapter describes Intel® IXP400 Software v2.0’s “Parity Error Notifier (IxParityENAcc) API” access-layer component.

16.1What’s New

This is a new component for software release 2.0.

Note: The PCI support described in this chapter is not supported in software release 2.0.

16.2Introduction

Many components in the IXP46X network processors provide parity error detection capabilities. These include:

•Instruction and Data Memory of the Network Processing Engines (NPEs)

•Switching Coprocessor in NPE B (SWCP)

•AHB Queue Manager SRAM (AQM)

•PCI Controller

•Expansion Bus Controller

•DDR SDRAM Memory Controller Unit (MCU). Additionally, the MCU on the IXP46X network processors provides Error Correction Code capabilities.

The IxParityENAcc access-layer component allows a client application to configure and enable/ disable the parity error detection the blocks listed above on the Intel® IXP46X Product Line of Network Processors. It enables a client application to receive notification when a parity error is detected, along with information on the type and source of the error.

16.2.1Background

The processor or its external memory could be operating in an environment where bits in memory may be corrupted by electromagnetic radiation. All the above-mentioned blocks can be affected by unexpected corruptions. Errors that are not the result of a permanent hardware error, but are encountered as random errors in the state of individual memory cells, are called “soft errors”. Parity and ECC are mechanisms to detect and provide corrective or restorative action from these soft errors.

Programmer’s Guide	IXP400 Software Version 2.0	April 2005
	Document Number: 252539, Revision: 007	233