Intel IXP400 manual 118

Intel® IXP400 Software

Contents

		8.6.1	IxDmaAccDescriptorManager		118
	8.7	Parameters Description			118
		8.7.1	Source Address		119
		8.7.2	Destination Address		119
		8.7.3	Transfer Mode		119
		8.7.4	Transfer Width		119
		8.7.5	Addressing Modes		120
		8.7.6	Transfer Length		120
		8.7.7	Supported Modes		121
	8.8	Data Flow			123
	8.9	Control Flow			123
		8.9.1	DMA Initialization		124
		8.9.2 DMA Configuration and Data Transfer			125
	8.10 Restrictions of the DMA Transfer				127
	8.11	Error Handling			128
	8.12	Little Endian			128
9	Access-Layer Components:
	Ethernet Access (IxEthAcc) API				129
	9.1	What’s New			129
	9.2	IxEthAcc Overview			129
	9.3	Ethernet Access Layers: Architectural Overview			130
		9.3.1 Role of the Ethernet NPE Microcode			130
		9.3.2	Queue Manager		131
		9.3.3	Learning/Filtering Database		131
		9.3.4	MAC/PHY Configuration		131
	9.4	Ethernet Access Layers: Component Features			132
	9.5	Data Plane			133
		9.5.1	Port Initialization		134
		9.5.2	Ethernet Frame Transmission		134
			9.5.2.1	Transmission Flow	134
			9.5.2.2 Transmit Buffer Management and Priority		135
			9.5.2.3	Using Chained IX_OSAL_MBUFs for Transmission / Buffer Sizing .... 137
		9.5.3	Ethernet Frame Reception		137
			9.5.3.1	Receive Flow	138
			9.5.3.2 Receive Buffer Management and Priority		139
			9.5.3.3 Additional Receive Path Information		142
		9.5.4	Data-Plane Endianness		143
		9.5.5 Maximum Ethernet Frame Size			143
	9.6	Control Path			143
		9.6.1	Ethernet MAC Control		145
			9.6.1.1	MAC Duplex Settings	145
			9.6.1.2	MII I/O	145
			9.6.1.3	Frame Check Sequence	145
			9.6.1.4	Frame Padding	145
			9.6.1.5	MAC Filtering	146
			9.6.1.6	802.3x Flow Control	146
			9.6.1.7	NPE Loopback	147
			9.6.1.8 Emergency Security Port Shutdown		147
	9.7	Initialization			147
	9.8	Shared Data Structures			147
April 2005				IXP400 Software Version 2.0	Programmer’s Guide
6				Document Number: 252539, Revision: 007