Intel® IXP400 Software

Access-Layer Components:

 

Synchronous Serial Port (IxSspAcc)

19

API

This chapter describes the Intel® IXP400 Software v2.0’s “SSP Serial Port (IxSspAcc) API” access-layer component.

19.1What’s New

This is a new component for software release 2.0.

19.2Introduction

A Synchronous Serial Port is included in the Intel® IXP46X Product Line of Network Processors. The IxSspAcc API is provided to allow the configuration of the various registers related to the SSP hardware. Once configured, the API also provides the ability to transfer data to the Tx FIFO and from the Rx FIFO. Both polling and interrupt modes are supported.

19.3IxSspAcc API Details

19.3.1Features

This component provides capabilities to:

select frame format – SSP, SPI, or Microwire*

select data sizes – 4 to 16 bits

select clock source – external or on-chip

configure serial clock rate – to drive a baud rate of 7.2 Kbps to 1.8432 Mbps (if internal clock source is selected only)

enable/disable the receive FIFO level interrupts

enable/disable the transmit FIFO level interrupts

set the transmit FIFO threshold – 1 to 16 frames

set the receive FIFO threshold – 1 to 16 frames

select operation mode – normal or loop-back operation

select SPI SCLK polarity – polarity of SCLK idle state is low or high (only used in SPI format)

Programmer’s Guide

IXP400 Software Version 2.0

April 2005

 

Document Number: 252539, Revision: 007

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Intel IXP400 manual Access-Layer Components Synchronous Serial Port IxSspAcc, IxSspAcc API Details