Intel IXP400 manual Summary Parity Error Notification Scenario, Parity Error Notification Sequence

Intel® IXP400 Software

Access-Layer Components: Parity Error Notifier (IxParityENAcc) API

•Parity Error Recovery

•Parity Error Prevention

This section summarizes the high-level activities involved with these high-level tasks, and then presents specific usage scenarios.

16.4.1Summary Parity Error Notification Scenario

The interface between the client application and IxParityENAcc is explained in detail in the API source-code documentation. However, the following important scenario (shown in Figure 76) captures the usage of interface(s) by the client application.

The parity error context is represented with the data flow direction arrow with an open bubble at the end. The numbers at the beginning of each of the APIs and internal steps define their execution sequence in that order.

Figure 76. Parity Error Notification Sequence

	Client
1: ixParityENAccInit (void)	6. ixParityENAccParityErrorInterruptClear(*pecMessage)
2. ixParityENAccCallbackRegister (parityErrNfyCallBack)
	5. ixParityENAccParityErrorContextGet(*pecMessage)
ixParityENAccParityDetectionConfigure(*hwParityConfig)
	4: (*ixParityENAccCallback ) (void)	Client Callback Routine
Client Application		(Parity Error Recovery)
2b: Save Callback
	3b: Get Callback
IxParityENAcc
	6b : interrupt clear or mask off
	5b : Fetch the parity error context
Access-Layer	3a: Invoke Parity Error Interrupt Handler
Hardware
	3: Parity Error Interrupt
Interrupt Controller /
Hardware Block
		B4384-01

1.The client application will initialize the component.

2.After initialization the client application will register callback and configure the parity error detection for the specified hardware blocks.

Programmer’s Guide	IXP400 Software Version 2.0	April 2005
	Document Number: 252539, Revision: 007	239