Intel® IXP400 Software
Access-Layer Components: HSS-Access (IxHssAcc) API
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
192 Document Number: 252539, Revision: 007
13.3.3 HSS and HDLC Theory and Coprocessor Operation
The HSS coprocessor enables the processor to communicate externally, in a serial-bit fashion,
using TDM data. The bit-stream protocols supported are T1, E1, and MVIP. The HSS coprocessor
also can interface with xDSL framers.
Figure 59. HSS/HDLC Access Overview
Intel X S ca le
®
Core
Packetized Client
IxHssAcc
NPE
Pack e tize d D a ta P ath
Send
Callback - Send Done / Receive
HDLC
Coprocessor
Control Path
Msging
Interf ace
Connect /Disconnect
Start/Stop
AHB Queue Manager
HSS 0
HSS 1
Callback Free Low
AHB Bus
NPE
IxNp eM h
HSS
Coprocessor
NPE A
Channelized Data Path
APB Bus
B2378-02
Ch a n n e lize d C lien t
IxQ Mg r