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Intel IXP400 manual HSS and Hdlc Theory and Coprocessor Operation, Intel X S cale C ore

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Intel® IXP400 Software

Access-Layer Components: HSS-Access (IxHssAcc) API

Figure 59. HSS/HDLC Access Overview

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13.3.3HSS and HDLC Theory and Coprocessor Operation

The HSS coprocessor enables the processor to communicate externally, in a serial-bit fashion, using TDM data. The bit-stream protocols supported are T1, E1, and MVIP. The HSS coprocessor also can interface with xDSL framers.

April 2005	IXP400 Software Version 2.0	Programmer’s Guide
192	Document Number: 252539, Revision: 007

Image 192

Intel IXP400 manual HSS and Hdlc Theory and Coprocessor Operation, Intel X S cale C ore

Contents

Intel IXP400 Software Programmer’s GuideIntel IXP400 Software IXP400 Software VersionContents 1.1 100 118 152 Contents Access-Layer Components 225 17.9 Operating System Adsl Driver Figures 102 Tables AQM 300 Revision History Date Revision DescriptionIntroduction1 Versions Supported by this DocumentHardware Supported by this Release Intended AudienceHow to Use this Document About the ProcessorsChapters Description Related Documents Document Title Document #Acronyms Document Title Document #Acronym Description CPU HSS MSB SIP Software Architecture Overview High-Level OverviewDeliverable Model Software Architecture OverviewAccess Library Source Code Documentation Operating System SupportDevelopment Tools Release Directory Structure Ixposal Include Src Ixp400xscalesw\---include +---npeMh Threading and Locking Policy Polled and Interrupt OperationStatistics and MIBs Global Dependency Chart Global DependenciesThis page is intentionally left blank Buffer Management What’s NewOverview Buffer Management Intel IXP400 Software Buffer FlowIxpbuf User Interface Raw BuffersIxpbuf Structure Ixpbuf Structure and MacrosOsal Ixpbuf structure and macros API User Interface to Ixpbuf Pool Management Fields Ixmbuf OS-Dependent Buffer FormatIxpbuf ixctrl Structure Ixne IXP400 NPE Shared StructureMapping of Ixmbuf to Shared Structure Ixpbuf NPE Shared StructureIxmbuf Structure Internal Ixmbuf Field Format Sheet 1Ixnext Ixosalmbufnextbufferinpktptr IxreservedField / Macro Purpose Used by Access-Layer? Internal Ixmbuf Field Format Sheet 2Ixmbuf Field Details Sheet 1 Mapping to OS Native Buffer Types VxWorks* Mblk BufferIxmbuf Field Details Sheet 2 Linux* skbuff Buffer Ixmbuf to Mblk MappingFollowing fields will get updated in the skbuffer Buffer Translation FunctionsCaching Strategy Tx PathRx Path Caching Strategy SummaryBuffer Management Tx Cache Flushing Example Intel IXP400 Software This page is intentionally left blank Access-Layer Components ATM Driver Access IxAtmdAcc API IxAtmdAcc Component FeaturesAccess-Layer Components ATM Driver Access IxAtmdAcc API Configuration Services Utopia Port-Configuration ServiceATM Traffic-Shaping Services VC-Configuration Services Transmission Services Scheduled Transmission Buffer Transmission for a Scheduled PortSchedule Table Description Transmission Triggers Tx-Low Notification Transmit-Done ProcessingTx Done Recycling Using a Threshold Level Transmit Done Based on a Threshold LevelTx Done Recycling Using a Polling Mechanism Transmit DisconnectReceive Services Tx DisconnectReceive Triggers Rx-Free-Low Notification Receive ProcessingReceive Based on a Threshold Level Rx Using a Threshold Level RX Using a Polling Mechanism Receive DisconnectBuffer Contents Buffer ManagementBuffer Allocation Ixpbuf Fields Required for Transmission Ixpbuf Fields of Available Buffers for ReceptionIxpbuf Fields Modified During Reception Sheet 1 Field DescriptionError Handling API-Usage ErrorsBuffer-Size Constraints Buffer-Chaining ConstraintsReal-Time Errors Real-Time ErrorsCause Consequences and Side Effects Corrective Action Access-Layer Components ATM Manager IxAtmm API IxAtmm Component FeaturesIxAtmm Overview Access-Layer Components ATM Manager IxAtmm API Utopia Level-2 Port InitializationATM-Port Management Service Model Services Provided by Ixatmm Tx/Rx Control Configuration Configuration of Traffic Control Mechanism Error Handling DependenciesManagement Interfaces Memory RequirementsPerformance Access-Layer Components ATM Transmit Scheduler IxAtmSch IxAtmSch Component FeaturesAccess-Layer Components ATM Transmit Scheduler IxAtmSch API Supported Traffic TypesTraffic Type Supported Num VCs Connection Admission Control CAC Function Scheduling and Traffic Shaping Schedule TableSchedule Service Model Minimum Cells Value minCellsToScheduleMaximum Cells Value maxCells Timing and Idle Cells Code Size Data MemoryIxAtmSch Data Memory Usage Per VC Data Per Port Data TotalLatency Access-Layer Components Security IxCryptoAcc API Access-Layer Components Security IxCryptoAcc API IxCryptoAcc API ArchitectureIxCryptoAcc Interfaces Basic API Flow Context Registration and the Cryptographic Context Database Basic IxCryptoAcc API FlowIntel IXP400 Software IxCryptoAcc API Call Process Flow for CCD Updates Buffer and Queue Management Memory RequirementsIxCryptoAcc Data Memory Usage Sheet 1 Structure Size in Bytes Total Size in BytesDependencies IxCryptoAcc Data Memory Usage Sheet 2Other API Functionality IxCryptoAccHashKeyGenerateIPSec Services EndiannessImport and Export of Cryptographic Technology IPSec Background and ImplementationIxCryptoAcc, NPE and IPSec Stack Scope IPSec Packet Formats Relationship Between IPSec Protocol and AlgorithmsAuthentication Header Reference ESP DataflowReference AH Dataflow ESP Data FlowHardware Acceleration for IPSec Services IPSec API Call FlowIPSec API Call Flow Special API Use Cases Hmac with Key Size Greater Than 64 BytesCCM Operation Flow AES CBC Encryption For MIC WEP Services IPSec Assumptions, Dependencies, and LimitationsWEP Background and Implementation Hardware Acceleration for WEP Services WEP Frame with Request ParametersWEP API Call Flow IxCryptoAccNpeWepPerformIxCryptoAccXscaleWepPerform NPE Microcode ImagesWEP Perform API Call Flow Authentication Combined Mode OperationsSSL and TLS Protocol Usage Models Encryption/DecryptionSupported Encryption and Authentication Algorithms Encryption AlgorithmsSupported Encryption Algorithms Cipher Key Sizes Parity Bit Actual Key SizeCounter Mode CTR Cipher ModesElectronic Code Book ECB Cipher Block Chaining CBCAuthentication Algorithms Supported Authentication AlgorithmsAuthentication Algorithm Data Block Size Bits Key Size Bits 114 Document Number 252539, Revision Access-Layer Components DMA Access Driver IxDmaAcc API FeaturesAssumptions DMA Access-Layer API Access-Layer Components DMA Access Driver IxDmaAcc APIIxDmaAcc Component Overview Parameters Description IxDmaAccDescriptorManagerTransfer Mode Source AddressDestination Address Transfer WidthAddressing Modes Transfer LengthTransfer Mode Supported ModesIncrement 122 Document Number 252539, Revision Data Flow Control FlowDMA Initialization IxDmaAcc Control FlowDMA Configuration and Data Transfer IxDMAcc InitializationDMA Transfer Operation Restrictions of the DMA Transfer Little Endian Access-Layer Components Ethernet Access IxEthAcc API IxEthAcc OverviewEthernet Access Layers Architectural Overview Access-Layer Components Ethernet Access IxEthAcc APIRole of the Ethernet NPE Microcode 4 MAC/PHY Configuration Queue ManagerLearning/Filtering Database Ethernet Access Layers Component Features Ethernet Access Layers Block Diagram Data PlanePort Initialization Ethernet Frame TransmissionTransmission Flow Transmit Buffer Management and Priority Ethernet Transmit Frame Data Buffer Flow TxEnetDoneUsing Chained IXOSALMBUFs for Transmission / Buffer Sizing Ethernet Frame ReceptionTx Fifo Priority Receive Flow Ethernet Receive Frame API OverviewReceive Buffer Management and Priority Buffer SizingSupplying Buffers Programmer’s Guide Codelet or client applicationRx Fifo Priority QoS Mode Freeing BuffersRecycling Buffers Additional Receive Path Information No Receive PollingControl Path Data-Plane EndiannessMaximum Ethernet Frame Size IxEthAcc and Secondary Components MAC Duplex Settings Ethernet MAC ControlMII I/O Frame Check SequencePromiscuous Mode Non-Promiscuous ModeMAC Filtering 1.6 802.3x Flow ControlInitialization Shared Data StructuresNPE Loopback Emergency Security Port ShutdownIxosalmbuf Structure Format Ixpneflags Field FormatQueue Field Description Eth 150 Document Number 252539, Revision Ixosalmbuf Port ID Field Format Management Information Ixosalmbuf Port ID Field ValuesIxpneflags.linkprot Field Values Field Bit ValuesManaged Objects for Ethernet Receive Object Increment CriteriaManaged Objects for Ethernet Transmit Access-Layer Components Ethernet Database IxEthDB API IxEthDB Functional BehaviorAccess-Layer Components Ethernet Database IxEthDB API MAC Address Learning and FilteringLearning and Filtering Node Learning/Filtering General Characteristics Other MAC Learning/Filtering Usage ModelsPort Definitions Port Dependency Map Provisioning Static and Dynamic EntriesAging Database Maintenance Frame Size FilteringRecord Management Source MAC Address Firewall Filtering Example Based Upon Maximum Frame SizeMAC Address Block/Admission 10.3.4 802.1Q Vlan Invalid MAC Address FilteringBackground Vlan Data in Ethernet Frames Untagged MAC Frame FormatVlan Tagged MAC Frame Format Database Records Associated With Vlan IDs Acceptable Frame Type FilteringVlan Tag Format Ingress Tagging and Tag Removal Port-Based Vlan Membership FilteringPort and VLAN-Based Egress Tagging and Tag Removal Special Conditions Tag Mode Frame Status Action Egress Vlan Tagging/Untagging Behavior Matrix10.3.5 802.1Q User Priority / QoS Support Port ID ExtractionPriority Aware Transmission Receive Priority Queuing QoS on Receive for 802.1Q Tagged FramesPriority to Traffic Class Mapping QoS on Receive for Untagged FramesDefault Priority to Traffic Class Mapping 10.3.6 802.3 / 802.11 Frame ConversionBackground 802.3 and 802.11 Frame Formats IEEE802.11 Frame FormatIEEE802.11 Frame Control FC Field Format AP-STA and AP-AP ModesHow the 802.3 / 802.11 Frame Conversion Feature Works Receive PathField AP to STA mode AP to AP mode To 802.11 Header Conversion RulesTransmit Path 10.3.6.3 802.3 / 802.11 API Details 11 to 802.3 Header Conversion RulesInput 802.11 Frame Values Output 802.3 Frame Field Values Frame TypeSpanning Tree Protocol Port Settings IxEthDB APIInitialization Feature Set Additional Database FeaturesIxEthDB Feature Set User-Defined FieldDependencies on IxEthAcc Configuration Database ClearPromiscuous-Mode Requirement FCS Appending180 Document Number 252539, Revision Access-Layer Components Ethernet PHY IxEthMii API Supported PHYsAccess-Layer Components Ethernet PHY IxEthMii API PHYs Supported by IxEthMiiAccess-Layer Components Feature Control IxFeatureCtrl API Hardware Feature ControlUsing the Product ID-Related Functions Access-Layer Components Feature Control IxFeatureCtrl APIProduct ID Values Bits DescriptionUsing the Feature Control Register Functions Feature Control Register Values Sheet 1Software Configuration Feature Control Register Values Sheet 2Component Check by Other APIs Document Number 252539, Revision 187 188 Document Number 252539, Revision Access-Layer Components HSS-Access IxHssAcc API Access-Layer Components HSS-Access IxHssAcc API Features IxHssAcc API OverviewIxHssAcc Interfaces Access-Layer Components HSS-Access IxHssAcc API HSS and Hdlc Theory and Coprocessor Operation Intel X S cale C oreHSS Output Clock Jitter and Error Characterization HSS Tx Clock Output frequencies and PPM ErrorHSS Tx Freq Pj Max ns Cj Max ns Aj Max ns Jitter Definitions HSS Frame Output CharacterizationJitter Type Jitter Definition Actual Frame Length µsHigh-Level API Call Flow Key Assumptions IxHssAcc Component DependenciesHSS Port Initialization Details IxHssAccPortInit198 Document Number 252539, Revision Channelized Connect and Enable HSS Channelized OperationIxHssAccChanConnect 200 Document Number 252539, Revision Channelized Tx/Rx Methods Channelized ConnectCallBack PolledChannelized Transmit and Receive Packetized Connect and Enable HSS Packetized OperationChannelized Disconnect IxHssAccPktPortConnectDocument Number 252539, Revision 205 Packetized Tx Packetized ConnectDocument Number 252539, Revision 207 Packetized Rx Packetized TransmitDocument Number 252539, Revision 209 Packetized Receive 13.6.5 56-Kbps, Packetized Raw Mode Data Flow in Packetized ServiceBuffer Allocation Data-Flow Overview Packetized Disconnect212 Document Number 252539, Revision HSS Packetized Receive Buffering Data Flow in Channelized Service HSS Packetized Transmit BufferingDocument Number 252539, Revision 215 HSS Channelized Receive Operation HSS Channelized Transmit Operation 218 Document Number 252539, Revision Access-Layer Components NPE-Downloader IxNpeDl API Microcode ImagesLoading NPE Microcode from a File Versus Loaded from Memory Access-Layer Components NPE-Downloader IxNpeDl API Standard Usage ExampleNPE Microcode Library Customization NPE Image CompatibilityNPE-A Images Image Name DescriptionNPE-B Images NPE-C Images Sheet 1Custom Usage Example IxNpeDl UninitializationNPE-C Images Sheet 2 Deprecated APIs Access-Layer Components NPE Message Handler IxNpeMh API Access-Layer Components NPE Message Handler IxNpeMh API Initializing the IxNpeMhInterrupt-Driven Operation Polled OperationUninitializing IxNpeMh Sending an NPE MessageSending an NPE Message with Response ClientCustomer / Demo Code IxNpeMhIxNpeMh Receiving Unsolicited Messages from NPE to Software Client Client Customer / Demo CodeIxNpeMh Component Dependencies 232 Document Number 252539, Revision Access-Layer Components Parity Error Notifier IxParityENAcc IntroductionBackground Network Processing Engines Scrubbing/Memory ScrubSwitching Coprocessor in NPE B Swcp AHB Queue Manager AQMDDR Sdram Memory Controller Unit MCU Expansion Bus ControllerParity Error Interrupts Interrupt Bit Default Priority SoftwareInterrupt Prioritization Secondary Effects of Parity InterruptsFeatures Feature Hardware Component Software Support RecoverableIxParityENAcc API Details IxParityENAcc Dependency Diagram IxParityENAcc API Usage ScenariosSummary Parity Error Notification Scenario Parity Error Notification SequenceParity Error Interrupt Deassertion Conditions Sheet 1 Interrupt Bit Source API Invoked bySummary Parity Error Recovery Scenario Parity Error Interrupt Deassertion Conditions Sheet 2Summary Parity Error Prevention Scenario Parity Error Notification Detailed ScenariosData Abort with No Parity Error Data Abort followed by Unrelated Parity Error Notification Data Abort Caused by Parity Error Data Abort with both Related and Unrelated Parity Errors Access-Layer Components Performance Profiling IxPerfProfAcc Intel XScale Core PMU Internal Bus PMU Counter Buffer OverflowIdle-Cycle Counter Utilities ‘Xcycle’ Interrupt Handling IxPerfProfAcc DependenciesUsing the API ThreadingAPI Usage for Intel XScale Core PMU Event and Clock Counting254 Document Number 252539, Revision Time-Based Sampling Display Performance CountersDisplay Clock Counter Event-Based Sampling Iii. Print out the first five elements258 Document Number 252539, Revision C0112788 No lower symbol found. Module kernel Using Intel XScale Core PMU to Determine Cache Efficiency Internal Bus PMU IxPerfProfAccBusPmuStart Xcycle Idlecycle Counter Perform the same calculation for the rest of the PECsDisplay Xcycle Measurement Access-Layer Components Queue Manager IxQMgr API Features and Hardware Interface Access-Layer Components Queue Manager IxQMgr APIDocument Number 252539, Revision 267 Configuration Values AQM Configuration AttributesDispatcher Attribute Description ValuesDispatcher Modes 270 Document Number 252539, Revision AQM Livelock Prevention Dispatcher in Context of a Polling MechanismDocument Number 252539, Revision 273 274 Document Number 252539, Revision Access-Layer Components Synchronous Serial Port IxSspAcc IxSspAcc API DetailsIxSspAcc Dependencies Interrupt Mode IxSspAcc API Usage ModelsInitialization and General Data Model 278 Document Number 252539, Revision Interrupt Scenario Polling Mode Init Transmit Receive 282 Document Number 252539, Revision Access-Layer Components Time Sync IxTimeSyncAcc API Access-Layer Components Time Sync IxTimeSyncAcc API Ieee 1588 PTP Protocol OverviewSynchronization Sequence Ieee 1588 Hardware Assist Block OverviewBlock Diagram of Intel IXP46X Network Processor Detailed InformationHardware Feature Options Default State IPv6 and VLAN-Tagged Ethernet FramesIxTimeSyncAcc API Details IxTimeSyncAccIeee 1588 PTP Client Application Additional Hardware InformationDocument Number 252539, Revision 289 Interrupt Mode Operations IxTimeSyncAcc API Usage ScenariosPolling for Transmit and Receive Timestamps Polled Mode Operations Interrupt Servicing of Target Time Reached ConditionPolling for Auxiliary Snapshot Values Access-Layer Components UART-Access IxUARTAcc API Interface DescriptionFifo Versus Polled Mode Access-Layer Components UART-Access IxUARTAcc APIUart / OS Dependencies Uart Services Models 296 Document Number 252539, Revision Access-Layer Components USB Access ixUSB API USB Controller BackgroundAccess-Layer Components USB Access ixUSB API IN, OUT, and Setup Token Packet FormatPacket Formats SOF Token Packet FormatTransaction Formats Data Packet FormatHandshake Packet Format Bits 023 BytesBulk Transaction Formats Isochronous Transaction FormatsAction Token Packet Data Packet Handshake Packet Action Token Packet Data PacketControl Write Setup Control Transaction Formats, Set-Up StageControl Transaction Formats Interrupt Transaction FormatsIxUSB Setup Requests API interfaces Available for Access LayerIxUSB API Interfaces Host-Device Request Summary Sheet 1 Request NameConfiguration Host-Device Request Summary Sheet 2IxUSB Endpoint Stall Feature IxUSB Send and Receive RequestsFrame Synchronization IxUSB Error Handling Stall on OUT TransactionsDetailed Error Codes Error due to unknown reasonsUSB Data Flow USB DependenciesCodelets ATM Codelet IxAtmCodeletCodelets Crypto Access Codelet IxCryptoAccCodelet DMA Access Codelet IxDmaAccCodeletEthernet Access Codelet IxEthAccCodelet Ethernet AAL-5 Codelet IxEthAal5AppHSS Access Codelet IxHssAccCodelet Parity Error Notifier Codelet IxParityENAccCodeletPerformance Profiling Codelet IxPerfProfAccCodelet Time Sync Codelet IxTimeSyncAccCodeletUSB Rndis Codelet IxUSBRNDIS Operating System Abstraction Layer Osal Operating System Abstraction Layer Osal Osal ArchitectureOS-Independent Core Module OS-Dependent ModuleCore Module Buffer Management ModuleOsal Library Structure Backward Compatibility ModuleBuffer Translation Module Document Number 252539, Revision 317 C lu d e Osal Modules and Related Interfaces Core ModuleIPC Osal Core Interface Sheet 1Thread Osal Core Interface Sheet 2Buffer Management Module 24.6.3 I/O Memory and Endianness Support ModuleOsal Buffer Management Interface Ixosalmmapvirttophys Osal I/O Memory and Endianness Interface Sheet 1Supporting a New OS Osal I/O Memory and Endianness Interface Sheet 2Supporting New Platforms Example 1. Global Memory Map DefinitionsIxstaticmap Adsl Driver Device SupportAdsl Driver Overview Adsl API Adsl Line Open/Close OverviewExample of Adsl Line Open Call Sequence Limitations and Constraints 2C Driver IxI2cDrv 26.3 I2C Driver API DetailsI2C Driver IxI2cDrv Arbitration Loss Error 2C Driver IxI2cDrvBus Error Master-Interrupt Mode26.4 I2C Driver API Usage Models InitializationI2C Driver IxI2cDrv Slave-Interrupt Mode Slave-Polling ModeSupport Functions Example Sequence Flows for Slave Mode Sequence Flow Diagram for Slave Transmit in Interrupt Mode Sequence Flow Diagram for Slave Receive in Polling Mode 26.4.3 I2C Using Gpio Versus Dedicated I2C Hardware Sequence Flow Diagram for Slave Transmit in Polling Mode340 Document Number 252539, Revision Endianness in Intel IXP400 Software Basics of EndiannessEndianness in Intel IXP400 Software Endianness When Memory is Shared Nature of Endianness Hardware or Software?Software Considerations and Implications Coding Pitfalls Little-Endian/Big-EndianCasting a Pointer Between Types of Different Sizes Network Stacks and Protocols Here is what the macro ntohl looks like in actual codeBest Practices in Coding of Endian-Independence Macro Examples Endian ConversionMacro Source Code Avoid346 Document Number 252539, Revision April Document Number 252539, Revision 347Supporting Little-Endian Mode Reasons for Choosing a Particular LE Coherency ModeHardware Switches Silicon Endianness ControlsIntel XScale Core Endianness Mode MMULittle-Endian Data Coherence Enable/Disable MMU P-Attribute BitByteswapen Bit Forcebyteswap BitSilicon Versions PCI Bus SwapSummary of Silicon Controls Endian Hardware SummaryIXP46X network processors A-0 stepping Part Number Brief DescriptionAPB Peripherals April 2005 Ethernet Access Component IxEthAcc NPE Downloader IxNpeDlNPE Message Handler IxNpeMh Data Plane Ixosalmbuf Data PayloadOne Half-Word-Aligned Ethernet Frame LE Address Coherent Intel XScale Core Read of IP Header LE Data Coherent Ethernet Access MIB Statistics Learning Database FunctionIntel IXP400 Software IxEthAcc and IxEthDB Summary 27.5.4 PCI Intel IXP400 Software OS AbstractionATM and HSS VxWorks* Considerations Intel IXP400 Software MacrosEndian Conversion Macros #definesVxWorks* Data Coherent Swap Code Software Versions Intel IXP400 Software VersionsIntel IXP400 Software Version Little-Endian Support Yes/No