Intel® IXP400 Software

Endianness in Intel® IXP400 Software

\vxworks\include\platforms\ixp400 \IxOsalOsIxp400CustomizedMappings.h. Further information on the VxWorks memory map is available in the VxWorks BSP documentation for the supported development platforms. Depending on their implementations, other operating systems may provide similar files/documents.

The macros shown in “Intel® IXP400 Software Macros” on page 362 are provided for use in the IXP400 software components. The defines are correct for software release 2.0, but may change for other releases.

Table 67. Intel® IXP400 Software Macros

#defines

#IX_OSAL_BE #IX_OSAL_LE_AC #IX_OSAL_LE_DC

Table 68 shows the endian conversion macros that need to be mapped for developer usage.

Table 68. Endian Conversion Macros

Macro

Behavior

Description

 

 

 

BE_XSTOBUSL()

No swap

Big-Endian XScale to Bus Long

 

 

 

BE_XSTOBUSS()

No swap

Big-Endian XScale to Bus Short

 

 

 

BE_BUSTOXSL()

No swap

Big-Endian Bus to XScale Long

 

 

 

BE_BUSTOXSS()

No swap

Big-Endian Bus to XScale Short

 

 

 

LE_AC_ XSTOBUSL()

No swap

Little-Endian Address Coherent XScale to Bus Long

 

 

 

LE_AC_

Address Swap

Little-Endian Address Coherent XScale to Bus Short

XSTOBUSS()

 

 

 

 

 

LE_AC_ BUSTOXSL()

No swap

Little-Endian Address Coherent Bus to XScale Long

 

 

 

LE_AC_

Address Swap

Little-Endian Address Coherent Bus to XScale Short

BUSTOXSS()

 

 

 

 

 

LE_DC_ XSTOBUSL()

Data Word swap

Little-Endian Data Coherent XScale to Bus Long

 

 

 

LE_DC_

½ Data Word swap

Little-Endian Data Coherent Bus to XScale Short

XSTOBUSS()

 

 

 

 

 

LE_DC_ BUSTOXSL()

Data Word swap

Little-Endian Data Coherent Bus to XScale Long

 

 

 

LE_DC_

½ Data Word swap

Little-Endian Data Coherent XScale to Bus Short

BUSTOXSS()

 

 

 

 

 

27.5.6VxWorks* Considerations

Both the AHB Queue Manager and NPE debug control registers (NPE message handler component ixNpeMh) are placed in Data Coherent Little-Endian mode. As the NPE debug registers are in APB space, and other APB registers are mapped in Address Coherent mode, a Data Coherent alias for the APB bus is defined.

April 2005

IXP400 Software Version 2.0

Programmer’s Guide

362

Document Number: 252539, Revision: 007

 

Page 362
Image 362
Intel manual VxWorks* Considerations, Intel IXP400 Software Macros, Endian Conversion Macros, #defines