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Intel IXP400 manual Device Support, Adsl Driver Overview

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	Intel® IXP400 Software
ADSL Driver	25

This chapter describes the ADSL driver for the Intel® IXDP425 / IXCDP1100 Development Platform and Intel® IXDP465 Development Platform that supports the STMicroelectronics* (formally Alcatel*) MTK-20150 ADSL chipset in the ADSL Termination Unit-Remote (ATU-R) mode of operation.

The ADSL driver is provided as a separate package along with the Intel® IXP400 Software v2.0.

25.1What’s New

There are no changes or enhancements to this component in software release 2.0.

25.2Device Support

STMicroelectronics MTK-20150 on the IXDP425 / IXCDP1100 platform. The MTK-20150 chipset is made up of MTC-20154 integrated analog front end and the MTC-20156 DMT/ATM digital modem and ADSL transceiver controller.

25.3ADSL Driver Overview

The two main interfaces to the ADSL chipset are:

•The parallel CTRL-E interface — via the processor’s expansion bus

•The ATM UTOPIA data path interface — via the processor’s UTOPIA interface

The ADSL driver only supports communication with the ADSL chipset via the CTRL-E interface. All data path communication (ATM UTOPIA) must be performed via the ATM Access Layer component of the IXP400 software.

The driver uses the CTRL-E interface to download the STMicroelectronics firmware, configure and monitor the status of the ADSL chipset. The advantage of downloading the firmware via the CTRL-E interface is that it removes the requirement for a separate flash for the STMicroelectronics ADSL chipset.

The driver provides an API to bring the ADSL line up in ATU-R mode. The line is configured to negotiate the best possible line rate, given the conditions of the local loop when the line is opened. The line rate is not renegotiated once the modems are in the “show-time” mode.

There is very little configuration information required to open an ATU-R line. Almost all line configuration parameters are supplied by the ATU-C side.

APIs are provided to take the modem off line and to check the state of the line to see if the modem is in “show-time” mode.

Programmer’s Guide	IXP400 Software Version 2.0	April 2005
	Document Number: 252539, Revision: 007	327

Image 327

Intel IXP400 manual Device Support, Adsl Driver Overview

Contents

Programmer’s Guide Intel IXP400 SoftwareIXP400 Software Version Intel IXP400 SoftwareContents 1.1 100 118 152 Contents Access-Layer Components 225 17.9 Operating System Adsl Driver Figures 102 Tables AQM 300 Date Revision Description Revision HistoryIntended Audience Introduction1Versions Supported by this Document Hardware Supported by this ReleaseHow to Use this Document About the ProcessorsChapters Description Document Title Document # Related DocumentsAcronyms Document Title Document #Acronym Description CPU HSS MSB SIP High-Level Overview Software Architecture OverviewSoftware Architecture Overview Deliverable ModelAccess Library Source Code Documentation Operating System SupportDevelopment Tools Ixposal Include Src Ixp400xscalesw Release Directory Structure\---include +---npeMh Threading and Locking Policy Polled and Interrupt OperationStatistics and MIBs Global Dependencies Global Dependency ChartThis page is intentionally left blank Buffer Management What’s NewOverview Intel IXP400 Software Buffer Flow Buffer ManagementRaw Buffers Ixpbuf User InterfaceIxpbuf Structure and Macros Ixpbuf StructureOsal Ixpbuf structure and macros API User Interface to Ixpbuf Ixmbuf OS-Dependent Buffer Format Pool Management FieldsIxne IXP400 NPE Shared Structure Ixpbuf ixctrl StructureIxpbuf NPE Shared Structure Mapping of Ixmbuf to Shared StructureIxreserved Ixmbuf StructureInternal Ixmbuf Field Format Sheet 1 Ixnext IxosalmbufnextbufferinpktptrField / Macro Purpose Used by Access-Layer? Internal Ixmbuf Field Format Sheet 2Ixmbuf Field Details Sheet 1 Mapping to OS Native Buffer Types VxWorks* Mblk BufferIxmbuf Field Details Sheet 2 Ixmbuf to Mblk Mapping Linux* skbuff BufferBuffer Translation Functions Following fields will get updated in the skbufferTx Path Caching StrategyRx Path Caching Strategy SummaryBuffer Management Tx Cache Flushing Example Intel IXP400 Software This page is intentionally left blank IxAtmdAcc Component Features Access-Layer Components ATM Driver Access IxAtmdAcc APIAccess-Layer Components ATM Driver Access IxAtmdAcc API Configuration Services Utopia Port-Configuration ServiceATM Traffic-Shaping Services VC-Configuration Services Transmission Services Buffer Transmission for a Scheduled Port Scheduled TransmissionSchedule Table Description Transmit-Done Processing Transmission Triggers Tx-Low NotificationTransmit Done Based on a Threshold Level Tx Done Recycling Using a Threshold LevelTransmit Disconnect Tx Done Recycling Using a Polling MechanismTx Disconnect Receive ServicesReceive Triggers Rx-Free-Low Notification Receive ProcessingReceive Based on a Threshold Level Rx Using a Threshold Level Receive Disconnect RX Using a Polling MechanismBuffer Contents Buffer ManagementBuffer Allocation Field Description Ixpbuf Fields Required for TransmissionIxpbuf Fields of Available Buffers for Reception Ixpbuf Fields Modified During Reception Sheet 1Buffer-Chaining Constraints Error HandlingAPI-Usage Errors Buffer-Size ConstraintsReal-Time Errors Real-Time ErrorsCause Consequences and Side Effects Corrective Action Access-Layer Components ATM Manager IxAtmm API IxAtmm Component FeaturesIxAtmm Overview Utopia Level-2 Port Initialization Access-Layer Components ATM Manager IxAtmm APIATM-Port Management Service Model Services Provided by Ixatmm Tx/Rx Control Configuration Configuration of Traffic Control Mechanism Memory Requirements Error HandlingDependencies Management InterfacesPerformance IxAtmSch Component Features Access-Layer Components ATM Transmit Scheduler IxAtmSchAccess-Layer Components ATM Transmit Scheduler IxAtmSch API Supported Traffic TypesTraffic Type Supported Num VCs Connection Admission Control CAC Function Schedule Table Scheduling and Traffic ShapingSchedule Service Model Minimum Cells Value minCellsToScheduleMaximum Cells Value maxCells Timing and Idle Cells Per VC Data Per Port Data Total Code SizeData Memory IxAtmSch Data Memory UsageLatency Access-Layer Components Security IxCryptoAcc API Access-Layer Components Security IxCryptoAcc API IxCryptoAcc API ArchitectureIxCryptoAcc Interfaces Basic API Flow Basic IxCryptoAcc API Flow Context Registration and the Cryptographic Context DatabaseIntel IXP400 Software IxCryptoAcc API Call Process Flow for CCD Updates Structure Size in Bytes Total Size in Bytes Buffer and Queue ManagementMemory Requirements IxCryptoAcc Data Memory Usage Sheet 1IxCryptoAcc Data Memory Usage Sheet 2 DependenciesIxCryptoAccHashKeyGenerate Other API FunctionalityIPSec Background and Implementation IPSec ServicesEndianness Import and Export of Cryptographic TechnologyIxCryptoAcc, NPE and IPSec Stack Scope Relationship Between IPSec Protocol and Algorithms IPSec Packet FormatsReference ESP Dataflow Authentication HeaderESP Data Flow Reference AH DataflowIPSec API Call Flow Hardware Acceleration for IPSec ServicesIPSec API Call Flow Hmac with Key Size Greater Than 64 Bytes Special API Use CasesCCM Operation Flow AES CBC Encryption For MIC WEP Services IPSec Assumptions, Dependencies, and LimitationsWEP Background and Implementation WEP Frame with Request Parameters Hardware Acceleration for WEP ServicesNPE Microcode Images WEP API Call FlowIxCryptoAccNpeWepPerform IxCryptoAccXscaleWepPerformWEP Perform API Call Flow Encryption/Decryption AuthenticationCombined Mode Operations SSL and TLS Protocol Usage ModelsCipher Key Sizes Parity Bit Actual Key Size Supported Encryption and Authentication AlgorithmsEncryption Algorithms Supported Encryption AlgorithmsCipher Block Chaining CBC Counter Mode CTRCipher Modes Electronic Code Book ECBAuthentication Algorithms Supported Authentication AlgorithmsAuthentication Algorithm Data Block Size Bits Key Size Bits 114 Document Number 252539, Revision Access-Layer Components DMA Access Driver IxDmaAcc API FeaturesAssumptions Access-Layer Components DMA Access Driver IxDmaAcc API DMA Access-Layer APIIxDmaAcc Component Overview IxDmaAccDescriptorManager Parameters DescriptionTransfer Width Transfer ModeSource Address Destination AddressTransfer Length Addressing ModesTransfer Mode Supported ModesIncrement 122 Document Number 252539, Revision Control Flow Data FlowIxDmaAcc Control Flow DMA InitializationIxDMAcc Initialization DMA Configuration and Data TransferDMA Transfer Operation Restrictions of the DMA Transfer Little Endian IxEthAcc Overview Access-Layer Components Ethernet Access IxEthAcc APIEthernet Access Layers Architectural Overview Access-Layer Components Ethernet Access IxEthAcc APIRole of the Ethernet NPE Microcode 4 MAC/PHY Configuration Queue ManagerLearning/Filtering Database Ethernet Access Layers Component Features Data Plane Ethernet Access Layers Block DiagramPort Initialization Ethernet Frame TransmissionTransmission Flow Transmit Buffer Management and Priority TxEnetDone Ethernet Transmit Frame Data Buffer FlowUsing Chained IXOSALMBUFs for Transmission / Buffer Sizing Ethernet Frame ReceptionTx Fifo Priority Ethernet Receive Frame API Overview Receive FlowReceive Buffer Management and Priority Buffer SizingSupplying Buffers Codelet or client application Programmer’s GuideRx Fifo Priority QoS Mode Freeing BuffersRecycling Buffers No Receive Polling Additional Receive Path InformationControl Path Data-Plane EndiannessMaximum Ethernet Frame Size IxEthAcc and Secondary Components Frame Check Sequence MAC Duplex SettingsEthernet MAC Control MII I/O1.6 802.3x Flow Control Promiscuous ModeNon-Promiscuous Mode MAC FilteringEmergency Security Port Shutdown InitializationShared Data Structures NPE LoopbackIxpneflags Field Format Ixosalmbuf Structure FormatQueue Field Description Eth 150 Document Number 252539, Revision Ixosalmbuf Port ID Field Format Field Bit Values Management InformationIxosalmbuf Port ID Field Values Ixpneflags.linkprot Field ValuesObject Increment Criteria Managed Objects for Ethernet ReceiveManaged Objects for Ethernet Transmit IxEthDB Functional Behavior Access-Layer Components Ethernet Database IxEthDB APIAccess-Layer Components Ethernet Database IxEthDB API MAC Address Learning and FilteringLearning and Filtering Node Learning/Filtering General Characteristics Other MAC Learning/Filtering Usage ModelsPort Definitions Port Dependency Map Provisioning Static and Dynamic EntriesAging Database Maintenance Frame Size FilteringRecord Management Source MAC Address Firewall Filtering Example Based Upon Maximum Frame SizeMAC Address Block/Admission Invalid MAC Address Filtering 10.3.4 802.1Q VlanBackground Vlan Data in Ethernet Frames Untagged MAC Frame FormatVlan Tagged MAC Frame Format Database Records Associated With Vlan IDs Acceptable Frame Type FilteringVlan Tag Format Port-Based Vlan Membership Filtering Ingress Tagging and Tag RemovalPort and VLAN-Based Egress Tagging and Tag Removal Special Conditions Egress Vlan Tagging/Untagging Behavior Matrix Tag Mode Frame Status Action10.3.5 802.1Q User Priority / QoS Support Port ID ExtractionPriority Aware Transmission QoS on Receive for 802.1Q Tagged Frames Receive Priority QueuingQoS on Receive for Untagged Frames Priority to Traffic Class MappingIEEE802.11 Frame Format Default Priority to Traffic Class Mapping10.3.6 802.3 / 802.11 Frame Conversion Background 802.3 and 802.11 Frame FormatsAP-STA and AP-AP Modes IEEE802.11 Frame Control FC Field FormatReceive Path How the 802.3 / 802.11 Frame Conversion Feature WorksField AP to STA mode AP to AP mode To 802.11 Header Conversion RulesTransmit Path Frame Type 10.3.6.3 802.3 / 802.11 API Details11 to 802.3 Header Conversion Rules Input 802.11 Frame Values Output 802.3 Frame Field ValuesSpanning Tree Protocol Port Settings IxEthDB APIInitialization User-Defined Field Feature SetAdditional Database Features IxEthDB Feature SetFCS Appending Dependencies on IxEthAcc ConfigurationDatabase Clear Promiscuous-Mode Requirement180 Document Number 252539, Revision Supported PHYs Access-Layer Components Ethernet PHY IxEthMii APIPHYs Supported by IxEthMii Access-Layer Components Ethernet PHY IxEthMii APIHardware Feature Control Access-Layer Components Feature Control IxFeatureCtrl APIBits Description Using the Product ID-Related FunctionsAccess-Layer Components Feature Control IxFeatureCtrl API Product ID ValuesFeature Control Register Values Sheet 1 Using the Feature Control Register FunctionsSoftware Configuration Feature Control Register Values Sheet 2Component Check by Other APIs Document Number 252539, Revision 187 188 Document Number 252539, Revision Access-Layer Components HSS-Access IxHssAcc API Access-Layer Components HSS-Access IxHssAcc API Features IxHssAcc API OverviewIxHssAcc Interfaces Access-Layer Components HSS-Access IxHssAcc API Intel X S cale C ore HSS and Hdlc Theory and Coprocessor OperationHSS Output Clock Jitter and Error Characterization HSS Tx Clock Output frequencies and PPM ErrorHSS Tx Freq Pj Max ns Cj Max ns Aj Max ns Actual Frame Length µs Jitter DefinitionsHSS Frame Output Characterization Jitter Type Jitter DefinitionHigh-Level API Call Flow IxHssAcc Component Dependencies Key AssumptionsIxHssAccPortInit HSS Port Initialization Details198 Document Number 252539, Revision Channelized Connect and Enable HSS Channelized OperationIxHssAccChanConnect 200 Document Number 252539, Revision Channelized Connect Channelized Tx/Rx MethodsPolled CallBackChannelized Transmit and Receive IxHssAccPktPortConnect Packetized Connect and EnableHSS Packetized Operation Channelized DisconnectDocument Number 252539, Revision 205 Packetized Connect Packetized TxDocument Number 252539, Revision 207 Packetized Transmit Packetized RxDocument Number 252539, Revision 209 Packetized Receive Packetized Disconnect 13.6.5 56-Kbps, Packetized Raw ModeData Flow in Packetized Service Buffer Allocation Data-Flow Overview212 Document Number 252539, Revision HSS Packetized Receive Buffering HSS Packetized Transmit Buffering Data Flow in Channelized ServiceDocument Number 252539, Revision 215 HSS Channelized Receive Operation HSS Channelized Transmit Operation 218 Document Number 252539, Revision Access-Layer Components NPE-Downloader IxNpeDl API Microcode ImagesLoading NPE Microcode from a File Versus Loaded from Memory NPE Image Compatibility Access-Layer Components NPE-Downloader IxNpeDl APIStandard Usage Example NPE Microcode Library CustomizationImage Name Description NPE-A ImagesNPE-C Images Sheet 1 NPE-B ImagesCustom Usage Example IxNpeDl UninitializationNPE-C Images Sheet 2 Deprecated APIs Access-Layer Components NPE Message Handler IxNpeMh API Polled Operation Access-Layer Components NPE Message Handler IxNpeMh APIInitializing the IxNpeMh Interrupt-Driven OperationSending an NPE Message Uninitializing IxNpeMhIxNpeMh Sending an NPE Message with ResponseClient Customer / Demo CodeIxNpeMh Client Customer / Demo Code Receiving Unsolicited Messages from NPE to Software ClientIxNpeMh Component Dependencies 232 Document Number 252539, Revision Access-Layer Components Parity Error Notifier IxParityENAcc IntroductionBackground Scrubbing/Memory Scrub Network Processing EnginesExpansion Bus Controller Switching Coprocessor in NPE B SwcpAHB Queue Manager AQM DDR Sdram Memory Controller Unit MCUSecondary Effects of Parity Interrupts Parity Error InterruptsInterrupt Bit Default Priority Software Interrupt PrioritizationFeatures Feature Hardware Component Software Support RecoverableIxParityENAcc API Details IxParityENAcc API Usage Scenarios IxParityENAcc Dependency DiagramParity Error Notification Sequence Summary Parity Error Notification ScenarioInterrupt Bit Source API Invoked by Parity Error Interrupt Deassertion Conditions Sheet 1Parity Error Interrupt Deassertion Conditions Sheet 2 Summary Parity Error Recovery ScenarioParity Error Notification Detailed Scenarios Summary Parity Error Prevention ScenarioData Abort with No Parity Error Data Abort followed by Unrelated Parity Error Notification Data Abort Caused by Parity Error Data Abort with both Related and Unrelated Parity Errors Access-Layer Components Performance Profiling IxPerfProfAcc Intel XScale Core PMU Counter Buffer Overflow Internal Bus PMUIdle-Cycle Counter Utilities ‘Xcycle’ IxPerfProfAcc Dependencies Interrupt HandlingThreading Using the APIEvent and Clock Counting API Usage for Intel XScale Core PMU254 Document Number 252539, Revision Display Performance Counters Time-Based SamplingDisplay Clock Counter Iii. Print out the first five elements Event-Based Sampling258 Document Number 252539, Revision C0112788 No lower symbol found. Module kernel Using Intel XScale Core PMU to Determine Cache Efficiency Internal Bus PMU IxPerfProfAccBusPmuStart Perform the same calculation for the rest of the PECs Xcycle Idlecycle CounterDisplay Xcycle Measurement Access-Layer Components Queue Manager IxQMgr API Access-Layer Components Queue Manager IxQMgr API Features and Hardware InterfaceDocument Number 252539, Revision 267 Attribute Description Values Configuration ValuesAQM Configuration Attributes DispatcherDispatcher Modes 270 Document Number 252539, Revision AQM Dispatcher in Context of a Polling Mechanism Livelock PreventionDocument Number 252539, Revision 273 274 Document Number 252539, Revision IxSspAcc API Details Access-Layer Components Synchronous Serial Port IxSspAccIxSspAcc Dependencies Interrupt Mode IxSspAcc API Usage ModelsInitialization and General Data Model 278 Document Number 252539, Revision Interrupt Scenario Polling Mode Init Transmit Receive 282 Document Number 252539, Revision Access-Layer Components Time Sync IxTimeSyncAcc API Access-Layer Components Time Sync IxTimeSyncAcc API Ieee 1588 PTP Protocol OverviewSynchronization Sequence Overview Ieee 1588 Hardware Assist BlockDetailed Information Block Diagram of Intel IXP46X Network ProcessorIPv6 and VLAN-Tagged Ethernet Frames Hardware Feature Options Default StateAdditional Hardware Information IxTimeSyncAcc API DetailsIxTimeSyncAcc Ieee 1588 PTP Client ApplicationDocument Number 252539, Revision 289 Interrupt Mode Operations IxTimeSyncAcc API Usage ScenariosPolling for Transmit and Receive Timestamps Interrupt Servicing of Target Time Reached Condition Polled Mode OperationsPolling for Auxiliary Snapshot Values Interface Description Access-Layer Components UART-Access IxUARTAcc APIFifo Versus Polled Mode Access-Layer Components UART-Access IxUARTAcc APIUart / OS Dependencies Uart Services Models 296 Document Number 252539, Revision USB Controller Background Access-Layer Components USB Access ixUSB APISOF Token Packet Format Access-Layer Components USB Access ixUSB APIIN, OUT, and Setup Token Packet Format Packet FormatsBits 023 Bytes Transaction FormatsData Packet Format Handshake Packet FormatAction Token Packet Data Packet Bulk Transaction FormatsIsochronous Transaction Formats Action Token Packet Data Packet Handshake PacketInterrupt Transaction Formats Control Write SetupControl Transaction Formats, Set-Up Stage Control Transaction FormatsIxUSB Setup Requests API interfaces Available for Access LayerIxUSB API Interfaces Request Name Host-Device Request Summary Sheet 1Host-Device Request Summary Sheet 2 ConfigurationIxUSB Endpoint Stall Feature IxUSB Send and Receive RequestsFrame Synchronization Stall on OUT Transactions IxUSB Error HandlingError due to unknown reasons Detailed Error CodesUSB Dependencies USB Data FlowCodelets ATM Codelet IxAtmCodeletCodelets Ethernet AAL-5 Codelet IxEthAal5App Crypto Access Codelet IxCryptoAccCodeletDMA Access Codelet IxDmaAccCodelet Ethernet Access Codelet IxEthAccCodeletParity Error Notifier Codelet IxParityENAccCodelet HSS Access Codelet IxHssAccCodeletPerformance Profiling Codelet IxPerfProfAccCodelet Time Sync Codelet IxTimeSyncAccCodeletUSB Rndis Codelet IxUSBRNDIS Operating System Abstraction Layer Osal Osal Architecture Operating System Abstraction Layer OsalBuffer Management Module OS-Independent Core ModuleOS-Dependent Module Core ModuleOsal Library Structure Backward Compatibility ModuleBuffer Translation Module Document Number 252539, Revision 317 C lu d e Core Module Osal Modules and Related InterfacesOsal Core Interface Sheet 1 IPCOsal Core Interface Sheet 2 ThreadBuffer Management Module 24.6.3 I/O Memory and Endianness Support ModuleOsal Buffer Management Interface Osal I/O Memory and Endianness Interface Sheet 1 IxosalmmapvirttophysOsal I/O Memory and Endianness Interface Sheet 2 Supporting a New OSExample 1. Global Memory Map Definitions Supporting New PlatformsIxstaticmap Adsl Driver Device SupportAdsl Driver Overview Adsl Line Open/Close Overview Adsl APIExample of Adsl Line Open Call Sequence Limitations and Constraints 26.3 I2C Driver API Details 2C Driver IxI2cDrvI2C Driver IxI2cDrv 2C Driver IxI2cDrv Arbitration Loss ErrorInitialization Bus ErrorMaster-Interrupt Mode 26.4 I2C Driver API Usage ModelsI2C Driver IxI2cDrv Slave-Interrupt Mode Slave-Polling ModeSupport Functions Example Sequence Flows for Slave Mode Sequence Flow Diagram for Slave Transmit in Interrupt Mode Sequence Flow Diagram for Slave Receive in Polling Mode Sequence Flow Diagram for Slave Transmit in Polling Mode 26.4.3 I2C Using Gpio Versus Dedicated I2C Hardware340 Document Number 252539, Revision Endianness in Intel IXP400 Software Basics of EndiannessEndianness in Intel IXP400 Software Nature of Endianness Hardware or Software? Endianness When Memory is SharedSoftware Considerations and Implications Coding Pitfalls Little-Endian/Big-EndianCasting a Pointer Between Types of Different Sizes Here is what the macro ntohl looks like in actual code Network Stacks and ProtocolsAvoid Best Practices in Coding of Endian-IndependenceMacro Examples Endian Conversion Macro Source Code346 Document Number 252539, Revision Document Number 252539, Revision 347 AprilReasons for Choosing a Particular LE Coherency Mode Supporting Little-Endian ModeSilicon Endianness Controls Hardware SwitchesMMU Intel XScale Core Endianness ModeForcebyteswap Bit Little-Endian Data Coherence Enable/DisableMMU P-Attribute Bit Byteswapen BitEndian Hardware Summary Silicon VersionsPCI Bus Swap Summary of Silicon ControlsPart Number Brief Description IXP46X network processors A-0 steppingAPB Peripherals April 2005 Ethernet Access Component IxEthAcc NPE Downloader IxNpeDlNPE Message Handler IxNpeMh Ixosalmbuf Data Payload Data PlaneOne Half-Word-Aligned Ethernet Frame LE Address Coherent Intel XScale Core Read of IP Header LE Data Coherent Ethernet Access MIB Statistics Learning Database FunctionIntel IXP400 Software IxEthAcc and IxEthDB Summary 27.5.4 PCI Intel IXP400 Software OS AbstractionATM and HSS #defines VxWorks* ConsiderationsIntel IXP400 Software Macros Endian Conversion MacrosVxWorks* Data Coherent Swap Code Software Versions Intel IXP400 Software VersionsIntel IXP400 Software Version Little-Endian Support Yes/No