Programmer’s Guide
Intel IXP400 Software
IXP400 Software Version
Intel IXP400 Software
Contents
1.1
100
118
152
Contents Access-Layer Components
225
17.9
Operating System
Adsl Driver
Figures
102
Tables
AQM
300
Date Revision Description
Revision History
Versions Supported by this Document
Introduction1
Hardware Supported by this Release
Intended Audience
Chapters Description
How to Use this Document
About the Processors
Document Title Document #
Related Documents
Acronym Description
Acronyms
Document Title Document #
CPU
HSS
MSB
SIP
High-Level Overview
Software Architecture Overview
Software Architecture Overview
Deliverable Model
Development Tools
Access Library Source Code Documentation
Operating System Support
Ixposal Include Src Ixp400xscalesw
Release Directory Structure
\---include +---npeMh
Statistics and MIBs
Threading and Locking Policy
Polled and Interrupt Operation
Global Dependencies
Global Dependency Chart
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Overview
Buffer Management
What’s New
Intel IXP400 Software Buffer Flow
Buffer Management
Raw Buffers
Ixpbuf User Interface
Ixpbuf Structure and Macros
Ixpbuf Structure
Osal Ixpbuf structure and macros
API User Interface to Ixpbuf
Ixmbuf OS-Dependent Buffer Format
Pool Management Fields
Ixne IXP400 NPE Shared Structure
Ixpbuf ixctrl Structure
Ixpbuf NPE Shared Structure
Mapping of Ixmbuf to Shared Structure
Internal Ixmbuf Field Format Sheet 1
Ixmbuf Structure
Ixnext Ixosalmbufnextbufferinpktptr
Ixreserved
Ixmbuf Field Details Sheet 1
Field / Macro Purpose Used by Access-Layer?
Internal Ixmbuf Field Format Sheet 2
Ixmbuf Field Details Sheet 2
Mapping to OS Native Buffer Types
VxWorks* Mblk Buffer
Ixmbuf to Mblk Mapping
Linux* skbuff Buffer
Buffer Translation Functions
Following fields will get updated in the skbuffer
Tx Path
Caching Strategy
Buffer Management Tx Cache Flushing Example
Rx Path
Caching Strategy Summary
Intel IXP400 Software
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IxAtmdAcc Component Features
Access-Layer Components ATM Driver Access IxAtmdAcc API
Access-Layer Components ATM Driver Access IxAtmdAcc API
ATM Traffic-Shaping Services
Configuration Services
Utopia Port-Configuration Service
VC-Configuration Services
Transmission Services
Buffer Transmission for a Scheduled Port
Scheduled Transmission
Schedule Table Description
Transmit-Done Processing
Transmission Triggers Tx-Low Notification
Transmit Done Based on a Threshold Level
Tx Done Recycling Using a Threshold Level
Transmit Disconnect
Tx Done Recycling Using a Polling Mechanism
Tx Disconnect
Receive Services
Receive Based on a Threshold Level
Receive Triggers Rx-Free-Low Notification
Receive Processing
Rx Using a Threshold Level
Receive Disconnect
RX Using a Polling Mechanism
Buffer Allocation
Buffer Contents
Buffer Management
Ixpbuf Fields of Available Buffers for Reception
Ixpbuf Fields Required for Transmission
Ixpbuf Fields Modified During Reception Sheet 1
Field Description
API-Usage Errors
Error Handling
Buffer-Size Constraints
Buffer-Chaining Constraints
Cause Consequences and Side Effects Corrective Action
Real-Time Errors
Real-Time Errors
IxAtmm Overview
Access-Layer Components ATM Manager IxAtmm API
IxAtmm Component Features
Utopia Level-2 Port Initialization
Access-Layer Components ATM Manager IxAtmm API
ATM-Port Management Service Model
Services Provided by Ixatmm
Tx/Rx Control Configuration
Configuration of Traffic Control Mechanism
Dependencies
Error Handling
Management Interfaces
Memory Requirements
Performance
IxAtmSch Component Features
Access-Layer Components ATM Transmit Scheduler IxAtmSch
Traffic Type Supported Num VCs
Access-Layer Components ATM Transmit Scheduler IxAtmSch API
Supported Traffic Types
Connection Admission Control CAC Function
Schedule Table
Scheduling and Traffic Shaping
Maximum Cells Value maxCells
Schedule Service Model
Minimum Cells Value minCellsToSchedule
Timing and Idle Cells
Data Memory
Code Size
IxAtmSch Data Memory Usage
Per VC Data Per Port Data Total
Latency
Access-Layer Components Security IxCryptoAcc API
IxCryptoAcc Interfaces
Access-Layer Components Security IxCryptoAcc API
IxCryptoAcc API Architecture
Basic API Flow
Basic IxCryptoAcc API Flow
Context Registration and the Cryptographic Context Database
Intel IXP400 Software
IxCryptoAcc API Call Process Flow for CCD Updates
Memory Requirements
Buffer and Queue Management
IxCryptoAcc Data Memory Usage Sheet 1
Structure Size in Bytes Total Size in Bytes
IxCryptoAcc Data Memory Usage Sheet 2
Dependencies
IxCryptoAccHashKeyGenerate
Other API Functionality
Endianness
IPSec Services
Import and Export of Cryptographic Technology
IPSec Background and Implementation
IxCryptoAcc, NPE and IPSec Stack Scope
Relationship Between IPSec Protocol and Algorithms
IPSec Packet Formats
Reference ESP Dataflow
Authentication Header
ESP Data Flow
Reference AH Dataflow
IPSec API Call Flow
Hardware Acceleration for IPSec Services
IPSec API Call Flow
Hmac with Key Size Greater Than 64 Bytes
Special API Use Cases
CCM Operation Flow
AES CBC Encryption For MIC
WEP Background and Implementation
WEP Services
IPSec Assumptions, Dependencies, and Limitations
WEP Frame with Request Parameters
Hardware Acceleration for WEP Services
IxCryptoAccNpeWepPerform
WEP API Call Flow
IxCryptoAccXscaleWepPerform
NPE Microcode Images
WEP Perform API Call Flow
Combined Mode Operations
Authentication
SSL and TLS Protocol Usage Models
Encryption/Decryption
Encryption Algorithms
Supported Encryption and Authentication Algorithms
Supported Encryption Algorithms
Cipher Key Sizes Parity Bit Actual Key Size
Cipher Modes
Counter Mode CTR
Electronic Code Book ECB
Cipher Block Chaining CBC
Authentication Algorithm Data Block Size Bits Key Size Bits
Authentication Algorithms
Supported Authentication Algorithms
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Assumptions
Access-Layer Components DMA Access Driver IxDmaAcc API
Features
Access-Layer Components DMA Access Driver IxDmaAcc API
DMA Access-Layer API
IxDmaAcc Component Overview
IxDmaAccDescriptorManager
Parameters Description
Source Address
Transfer Mode
Destination Address
Transfer Width
Transfer Length
Addressing Modes
Increment
Transfer Mode
Supported Modes
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Control Flow
Data Flow
IxDmaAcc Control Flow
DMA Initialization
IxDMAcc Initialization
DMA Configuration and Data Transfer
DMA Transfer Operation
Restrictions of the DMA Transfer
Little Endian
IxEthAcc Overview
Access-Layer Components Ethernet Access IxEthAcc API
Role of the Ethernet NPE Microcode
Ethernet Access Layers Architectural Overview
Access-Layer Components Ethernet Access IxEthAcc API
Learning/Filtering Database
4 MAC/PHY Configuration
Queue Manager
Ethernet Access Layers Component Features
Data Plane
Ethernet Access Layers Block Diagram
Transmission Flow
Port Initialization
Ethernet Frame Transmission
Transmit Buffer Management and Priority
TxEnetDone
Ethernet Transmit Frame Data Buffer Flow
Tx Fifo Priority
Using Chained IXOSALMBUFs for Transmission / Buffer Sizing
Ethernet Frame Reception
Ethernet Receive Frame API Overview
Receive Flow
Supplying Buffers
Receive Buffer Management and Priority
Buffer Sizing
Codelet or client application
Programmer’s Guide
Recycling Buffers
Rx Fifo Priority QoS Mode
Freeing Buffers
No Receive Polling
Additional Receive Path Information
Maximum Ethernet Frame Size
Control Path
Data-Plane Endianness
IxEthAcc and Secondary Components
Ethernet MAC Control
MAC Duplex Settings
MII I/O
Frame Check Sequence
Non-Promiscuous Mode
Promiscuous Mode
MAC Filtering
1.6 802.3x Flow Control
Shared Data Structures
Initialization
NPE Loopback
Emergency Security Port Shutdown
Ixpneflags Field Format
Ixosalmbuf Structure Format
Queue Field Description Eth
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Ixosalmbuf Port ID Field Format
Ixosalmbuf Port ID Field Values
Management Information
Ixpneflags.linkprot Field Values
Field Bit Values
Object Increment Criteria
Managed Objects for Ethernet Receive
Managed Objects for Ethernet Transmit
IxEthDB Functional Behavior
Access-Layer Components Ethernet Database IxEthDB API
Learning and Filtering
Access-Layer Components Ethernet Database IxEthDB API
MAC Address Learning and Filtering
Node
Port Definitions
Learning/Filtering General Characteristics
Other MAC Learning/Filtering Usage Models
Aging
Port Dependency Map
Provisioning Static and Dynamic Entries
Record Management
Database Maintenance
Frame Size Filtering
MAC Address Block/Admission
Source MAC Address Firewall
Filtering Example Based Upon Maximum Frame Size
Invalid MAC Address Filtering
10.3.4 802.1Q Vlan
Vlan Tagged MAC Frame Format
Background Vlan Data in Ethernet Frames
Untagged MAC Frame Format
Vlan Tag Format
Database Records Associated With Vlan IDs
Acceptable Frame Type Filtering
Port-Based Vlan Membership Filtering
Ingress Tagging and Tag Removal
Port and VLAN-Based Egress Tagging and Tag Removal
Special Conditions
Egress Vlan Tagging/Untagging Behavior Matrix
Tag Mode Frame Status Action
Priority Aware Transmission
10.3.5 802.1Q User Priority / QoS Support
Port ID Extraction
QoS on Receive for 802.1Q Tagged Frames
Receive Priority Queuing
QoS on Receive for Untagged Frames
Priority to Traffic Class Mapping
10.3.6 802.3 / 802.11 Frame Conversion
Default Priority to Traffic Class Mapping
Background 802.3 and 802.11 Frame Formats
IEEE802.11 Frame Format
AP-STA and AP-AP Modes
IEEE802.11 Frame Control FC Field Format
Receive Path
How the 802.3 / 802.11 Frame Conversion Feature Works
Transmit Path
Field AP to STA mode AP to AP mode
To 802.11 Header Conversion Rules
11 to 802.3 Header Conversion Rules
10.3.6.3 802.3 / 802.11 API Details
Input 802.11 Frame Values Output 802.3 Frame Field Values
Frame Type
Initialization
Spanning Tree Protocol Port Settings
IxEthDB API
Additional Database Features
Feature Set
IxEthDB Feature Set
User-Defined Field
Database Clear
Dependencies on IxEthAcc Configuration
Promiscuous-Mode Requirement
FCS Appending
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Supported PHYs
Access-Layer Components Ethernet PHY IxEthMii API
PHYs Supported by IxEthMii
Access-Layer Components Ethernet PHY IxEthMii API
Hardware Feature Control
Access-Layer Components Feature Control IxFeatureCtrl API
Access-Layer Components Feature Control IxFeatureCtrl API
Using the Product ID-Related Functions
Product ID Values
Bits Description
Feature Control Register Values Sheet 1
Using the Feature Control Register Functions
Component Check by Other APIs
Software Configuration
Feature Control Register Values Sheet 2
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Access-Layer Components HSS-Access IxHssAcc API
IxHssAcc Interfaces
Access-Layer Components HSS-Access IxHssAcc API Features
IxHssAcc API Overview
Access-Layer Components HSS-Access IxHssAcc API
Intel X S cale C ore
HSS and Hdlc Theory and Coprocessor Operation
HSS Tx Freq Pj Max ns Cj Max ns Aj Max ns
HSS Output Clock Jitter and Error Characterization
HSS Tx Clock Output frequencies and PPM Error
HSS Frame Output Characterization
Jitter Definitions
Jitter Type Jitter Definition
Actual Frame Length µs
High-Level API Call Flow
IxHssAcc Component Dependencies
Key Assumptions
IxHssAccPortInit
HSS Port Initialization Details
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IxHssAccChanConnect
Channelized Connect and Enable
HSS Channelized Operation
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Channelized Connect
Channelized Tx/Rx Methods
Polled
CallBack
Channelized Transmit and Receive
HSS Packetized Operation
Packetized Connect and Enable
Channelized Disconnect
IxHssAccPktPortConnect
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Packetized Connect
Packetized Tx
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Packetized Transmit
Packetized Rx
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Packetized Receive
Data Flow in Packetized Service
13.6.5 56-Kbps, Packetized Raw Mode
Buffer Allocation Data-Flow Overview
Packetized Disconnect
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HSS Packetized Receive Buffering
HSS Packetized Transmit Buffering
Data Flow in Channelized Service
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HSS Channelized Receive Operation
HSS Channelized Transmit Operation
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Loading NPE Microcode from a File Versus Loaded from Memory
Access-Layer Components NPE-Downloader IxNpeDl API
Microcode Images
Standard Usage Example
Access-Layer Components NPE-Downloader IxNpeDl API
NPE Microcode Library Customization
NPE Image Compatibility
Image Name Description
NPE-A Images
NPE-C Images Sheet 1
NPE-B Images
NPE-C Images Sheet 2
Custom Usage Example
IxNpeDl Uninitialization
Deprecated APIs
Access-Layer Components NPE Message Handler IxNpeMh API
Initializing the IxNpeMh
Access-Layer Components NPE Message Handler IxNpeMh API
Interrupt-Driven Operation
Polled Operation
Sending an NPE Message
Uninitializing IxNpeMh
Client
Sending an NPE Message with Response
Customer / Demo Code
IxNpeMh
IxNpeMh
Client Customer / Demo Code
Receiving Unsolicited Messages from NPE to Software Client
IxNpeMh Component Dependencies
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Background
Access-Layer Components Parity Error Notifier IxParityENAcc
Introduction
Scrubbing/Memory Scrub
Network Processing Engines
AHB Queue Manager AQM
Switching Coprocessor in NPE B Swcp
DDR Sdram Memory Controller Unit MCU
Expansion Bus Controller
Interrupt Bit Default Priority Software
Parity Error Interrupts
Interrupt Prioritization
Secondary Effects of Parity Interrupts
IxParityENAcc API Details
Features
Feature Hardware Component Software Support Recoverable
IxParityENAcc API Usage Scenarios
IxParityENAcc Dependency Diagram
Parity Error Notification Sequence
Summary Parity Error Notification Scenario
Interrupt Bit Source API Invoked by
Parity Error Interrupt Deassertion Conditions Sheet 1
Parity Error Interrupt Deassertion Conditions Sheet 2
Summary Parity Error Recovery Scenario
Parity Error Notification Detailed Scenarios
Summary Parity Error Prevention Scenario
Data Abort with No Parity Error
Data Abort followed by Unrelated Parity Error Notification
Data Abort Caused by Parity Error
Data Abort with both Related and Unrelated Parity Errors
Access-Layer Components Performance Profiling IxPerfProfAcc
Intel XScale Core PMU
Counter Buffer Overflow
Internal Bus PMU
Idle-Cycle Counter Utilities ‘Xcycle’
IxPerfProfAcc Dependencies
Interrupt Handling
Threading
Using the API
Event and Clock Counting
API Usage for Intel XScale Core PMU
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Display Performance Counters
Time-Based Sampling
Display Clock Counter
Iii. Print out the first five elements
Event-Based Sampling
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C0112788 No lower symbol found. Module kernel
Using Intel XScale Core PMU to Determine Cache Efficiency
Internal Bus PMU
IxPerfProfAccBusPmuStart
Perform the same calculation for the rest of the PECs
Xcycle Idlecycle Counter
Display Xcycle Measurement
Access-Layer Components Queue Manager IxQMgr API
Access-Layer Components Queue Manager IxQMgr API
Features and Hardware Interface
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AQM Configuration Attributes
Configuration Values
Dispatcher
Attribute Description Values
Dispatcher Modes
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AQM
Dispatcher in Context of a Polling Mechanism
Livelock Prevention
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IxSspAcc API Details
Access-Layer Components Synchronous Serial Port IxSspAcc
IxSspAcc Dependencies
Initialization and General Data Model
Interrupt Mode
IxSspAcc API Usage Models
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Interrupt Scenario
Polling Mode
Init Transmit Receive
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Access-Layer Components Time Sync IxTimeSyncAcc API
Synchronization Sequence
Access-Layer Components Time Sync IxTimeSyncAcc API
Ieee 1588 PTP Protocol Overview
Overview
Ieee 1588 Hardware Assist Block
Detailed Information
Block Diagram of Intel IXP46X Network Processor
IPv6 and VLAN-Tagged Ethernet Frames
Hardware Feature Options Default State
IxTimeSyncAcc
IxTimeSyncAcc API Details
Ieee 1588 PTP Client Application
Additional Hardware Information
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Polling for Transmit and Receive Timestamps
Interrupt Mode Operations
IxTimeSyncAcc API Usage Scenarios
Interrupt Servicing of Target Time Reached Condition
Polled Mode Operations
Polling for Auxiliary Snapshot Values
Interface Description
Access-Layer Components UART-Access IxUARTAcc API
Uart / OS Dependencies
Fifo Versus Polled Mode
Access-Layer Components UART-Access IxUARTAcc API
Uart Services Models
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USB Controller Background
Access-Layer Components USB Access ixUSB API
IN, OUT, and Setup Token Packet Format
Access-Layer Components USB Access ixUSB API
Packet Formats
SOF Token Packet Format
Data Packet Format
Transaction Formats
Handshake Packet Format
Bits 023 Bytes
Isochronous Transaction Formats
Bulk Transaction Formats
Action Token Packet Data Packet Handshake Packet
Action Token Packet Data Packet
Control Transaction Formats, Set-Up Stage
Control Write Setup
Control Transaction Formats
Interrupt Transaction Formats
IxUSB API Interfaces
IxUSB Setup Requests
API interfaces Available for Access Layer
Request Name
Host-Device Request Summary Sheet 1
Host-Device Request Summary Sheet 2
Configuration
Frame Synchronization
IxUSB Endpoint Stall Feature
IxUSB Send and Receive Requests
Stall on OUT Transactions
IxUSB Error Handling
Error due to unknown reasons
Detailed Error Codes
USB Dependencies
USB Data Flow
Codelets
Codelets
ATM Codelet IxAtmCodelet
DMA Access Codelet IxDmaAccCodelet
Crypto Access Codelet IxCryptoAccCodelet
Ethernet Access Codelet IxEthAccCodelet
Ethernet AAL-5 Codelet IxEthAal5App
Parity Error Notifier Codelet IxParityENAccCodelet
HSS Access Codelet IxHssAccCodelet
USB Rndis Codelet IxUSBRNDIS
Performance Profiling Codelet IxPerfProfAccCodelet
Time Sync Codelet IxTimeSyncAccCodelet
Operating System Abstraction Layer Osal
Osal Architecture
Operating System Abstraction Layer Osal
OS-Dependent Module
OS-Independent Core Module
Core Module
Buffer Management Module
Buffer Translation Module
Osal Library Structure
Backward Compatibility Module
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C lu d e
Core Module
Osal Modules and Related Interfaces
Osal Core Interface Sheet 1
IPC
Osal Core Interface Sheet 2
Thread
Osal Buffer Management Interface
Buffer Management Module
24.6.3 I/O Memory and Endianness Support Module
Osal I/O Memory and Endianness Interface Sheet 1
Ixosalmmapvirttophys
Osal I/O Memory and Endianness Interface Sheet 2
Supporting a New OS
Example 1. Global Memory Map Definitions
Supporting New Platforms
Ixstaticmap
Adsl Driver Overview
Adsl Driver
Device Support
Adsl Line Open/Close Overview
Adsl API
Example of Adsl Line Open Call Sequence
Limitations and Constraints
26.3 I2C Driver API Details
2C Driver IxI2cDrv
I2C Driver IxI2cDrv
2C Driver IxI2cDrv
Arbitration Loss Error
Master-Interrupt Mode
Bus Error
26.4 I2C Driver API Usage Models
Initialization
Support Functions
I2C Driver IxI2cDrv Slave-Interrupt Mode
Slave-Polling Mode
Example Sequence Flows for Slave Mode
Sequence Flow Diagram for Slave Transmit in Interrupt Mode
Sequence Flow Diagram for Slave Receive in Polling Mode
Sequence Flow Diagram for Slave Transmit in Polling Mode
26.4.3 I2C Using Gpio Versus Dedicated I2C Hardware
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Endianness in Intel IXP400 Software
Endianness in Intel IXP400 Software
Basics of Endianness
Nature of Endianness Hardware or Software?
Endianness When Memory is Shared
Casting a Pointer Between Types of Different Sizes
Software Considerations and Implications
Coding Pitfalls Little-Endian/Big-Endian
Here is what the macro ntohl looks like in actual code
Network Stacks and Protocols
Macro Examples Endian Conversion
Best Practices in Coding of Endian-Independence
Macro Source Code
Avoid
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April
Reasons for Choosing a Particular LE Coherency Mode
Supporting Little-Endian Mode
Silicon Endianness Controls
Hardware Switches
MMU
Intel XScale Core Endianness Mode
MMU P-Attribute Bit
Little-Endian Data Coherence Enable/Disable
Byteswapen Bit
Forcebyteswap Bit
PCI Bus Swap
Silicon Versions
Summary of Silicon Controls
Endian Hardware Summary
Part Number Brief Description
IXP46X network processors A-0 stepping
APB Peripherals
April 2005
NPE Message Handler IxNpeMh
Ethernet Access Component IxEthAcc
NPE Downloader IxNpeDl
Ixosalmbuf Data Payload
Data Plane
One Half-Word-Aligned Ethernet Frame LE Address Coherent
Intel XScale Core Read of IP Header LE Data Coherent
Intel IXP400 Software IxEthAcc and IxEthDB Summary
Ethernet Access MIB Statistics
Learning Database Function
ATM and HSS
27.5.4 PCI
Intel IXP400 Software OS Abstraction
Intel IXP400 Software Macros
VxWorks* Considerations
Endian Conversion Macros
#defines
VxWorks* Data Coherent Swap Code
Intel IXP400 Software Version Little-Endian Support Yes/No
Software Versions
Intel IXP400 Software Versions