Intel IXP400 manual Block Diagram of Intel IXP46X Network Processor, Detailed Information

Intel® IXP400 Software

Access-Layer Components: Time Sync (IxTimeSyncAcc) API

Figure 96 shows the location of the IEEE 1588 Hardware Assist block and its main interconnects to other components in the IXP46X network processors.

Figure 96. Block Diagram of Intel® IXP46X Network Processor

	MII
			NPE A
	MII		NPE B
			AHB/AHB	DDR Memory
	MII		Bridge	Controller
			NPE C
	IEEE 1588		AHB/APB	Queue
				Manager
			Bridge
Auxiliary Master
Snapshot	GPIO			Expansion
Auxiliary Slave		PMU		Bus Controller
			Intel
Snapshot
	UART	Timer	Xscale®
			Core	PCI
				Controller
	UART	Interrupt
		Ctrl	DMA
				USB
			Engine
				Controller
				B4395-01

Detailed Information

The IEEE 1588 Hardware Assist block implements a 64-bit register to keep track of the system time, which is used to provide timestamp references for PTP messages. The register is incremented based on a frequency scaling value, as supplied by the client application. The frequency scaling value is accumulated on every clock cycle in the system into a 32-bit register, and an overflow condition will cause the system time to increment. Thus, the slave will make use of the system time to synchronize with that of the master by adjusting the frequency scaling value based on the difference between the local system time and the master system time.

The IEEE 1588 Hardware Assist block also implements a mechanism whereby the system timer can be verified against a predefined target time for equals or exceeds conditions. Upon these conditions, the hardware block can interrupt the Intel XScale core, unless the interrupt is masked off. If the interrupt is masked off, the said condition is flagged. This interrupt or event may be used by client applications to update the frequency scaling and/or to set new system time and target time values. However, it is not mandatory to make use of this hardware feature to enable timestamping.

A timestamp may be generated for each of the channels (i.e., on both incoming and outgoing MII ports of an NPE) whenever the Sync and Delay_Req messages are detected (i.e., sent or received). These timestamps are captured into respective transmit or receive snapshot registers.

Corresponding event flags are set and will be locked unless no errors are encountered. They can be reset by clearing their corresponding events.

April 2005	IXP400 Software Version 2.0	Programmer’s Guide
286	Document Number: 252539, Revision: 007