Intel IXP400 Supporting Little-Endian Mode, Reasons for Choosing a Particular LE Coherency Mode

Intel® IXP400 Software

Endianness in Intel® IXP400 Software

27.4.1Supporting Little-Endian Mode

The following hardware items can be configured by software:

•Intel XScale core running under Little- or Big-Endian mode.

•The byte-swapping hardware in the PCI controller turned on or off.

The following hardware items cannot be changed by software or off-chip hardware (i.e. board design):

•AHB bus is running under Big-Endian mode.

•NPEs are running in Big-Endian mode relative to their own memory, and relative to AHB memory.

By default, the IXP400 software is designed to operate in Big-Endian mode and configures the Intel XScale core and PCI controller as such.

Given the above hardware design, supporting Little-Endian in the IXP4XX processors while using the Intel® IXP400 Software requires the following changes in hardware:

•The Intel XScale core is left to its standard default configuration, which is Little-Endian mode.

•The byte-swapping hardware in PCI controller is turned off by setting the following register values: pci_csr_ads=0, pci_csr_pds=0, pci_csr_abe=1. The Intel® IXP400 Software sets the following values to support the default Big-Endian operation: pci_csr_ads=1, pci_csr_pds=1, pci_csr_abe=1.

When the changes outlined above are applied, the Intel XScale core will run under Little-Endian mode while other processors in the system (for example, the NPEs) remain running under the same endian mode as defined in IXP400 software. The result is that the IXP4XX processor is running as an endian-hybrid system.

The information outlined above is a simplification of the options available in the IXP4XX product line and IXC1100 control plane processors, but does cover the basic concepts. Further detail is provided in following sections.

27.4.2Reasons for Choosing a Particular LE Coherency Mode

Little-Endian mode is sub-divided into two categories:

•Intel XScale core operating in Address Coherent mode

•Intel XScale core operating in Data Coherent mode

Both Address and Data Coherent endian conversion are provided because there are different benefits and hazards to both approaches. If the only goal of the endian conversion was to make the Intel XScale core self-consistent, meaning that the Intel XScale core properly reads what it wrote, then either method would be sufficient. However, since the Intel XScale core must communicate with other processors and interfaces within the IXP4XX processor, it is beneficial to provide both methods.

To understand this, consider the benefits and hazards of both approaches by examining the details of how data is stored in memory. In particular, how will the NPE read and interpret the data stored in memory? When the Intel XScale core is in Big-Endian mode, the NPE reads the data in the same format that it was written.

April 2005	IXP400 Software Version 2.0	Programmer’s Guide
348	Document Number: 252539, Revision: 007