Intel IXP400 manual Intel XScale Core Endianness Mode, Mmu

Intel® IXP400 Software

Endianness in Intel® IXP400 Software

Figure 116. Intel® IXP4XX Product Line of Network Processors and IXC1100 Control Plane Processor Endianness Controls

NPEs

NPEs

NPE’s

NPE’sNPE’s

NPE’s

MMU

MMU

Tables

Tables

( c

P o

Bus

- n L

t

B r E

i

o

t

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Addr/Data

Bus

®

Core

Addr/data

Cache

Bus

Memory

Subsystem

Intel XScale

®

Intel XScale ®

bus

Memory

Subsystem

®

Intel XScale

Core

Cache

(SDRAM)

Intel XScale

Endianness

(SDRAM)

Core

Endianness

Core

Conversion

logic

Conversion

logic

XScale LE

Bus

Expansion

CtrlCFG2

PCI Endianness sw ap

PCI Controller

control

PCI Controller

Under

softw are

PCIBus

control

B3810-001

B3810-001

27.4.3.2Intel XScale® Core Endianness Mode

The Big- and Little-Endian modes are controlled by the B-bit, located in the “Intel StrongARM Control Register”, coprocessor 15, register 1, bit 7. The default mode at reset is Little-endian. To enable the Big-Endian mode, the B bit must be set before performing any sub-word accesses to memory, or undefined results would occur. The bit takes effect even if the MMU is disabled. The following is assembly code to enable/clear the B-bit.

MACRO LITTLEENDIAN

MRC p15,0,a1,c1,c0,0

BIC a1,a1,#0x80 ;clear bit7 of register1 cp15

MCR p15,0,a1,c1,c0,0

ENDM

MACRO BIGENDIAN

MRC p15,0,a1,c1,c0,0

ORR a1,a1,#0x80 ;set bit7 of register1 cp15

April 2005	IXP400 Software Version 2.0	Programmer’s Guide
350	Document Number: 252539, Revision: 007