Intel IXP400 manual Learning Database Function, Ethernet Access MIB Statistics

Intel® IXP400 Software

Endianness in Intel® IXP400 Software

Figure 119. Intel XScale® Core Read of IP Header (LE Data Coherent) (Continued)

16-bit Identif (swapped)		flag/Fragment offset (swap)
TTL	Protocol	header checksum(swapped)
src-ip[3]	Src-ip[2]	src-ip[1]	src-ip[0]
dst-ip[3]	Dst-ip[2]	dst-ip[1]	dst-ip[0]

UDP/TCP Header

803.2Destination MAC Address

802.3Source MAC Address

802.3Type

Internet Protocol

UDP/TCP Header

Figure 119 shows that the IP protocol stack operates correctly with the payload offered to the stack for half-word-aligned ix_data using Data Coherent Little-Endian mode and the IP protocol stack’s use of data conversion macros.

27.5.3.4.3Learning Database Function

There are two main communication mechanisms between the Ethernet NPEs and the Intel XScale core Ethernet learning function:

•NPE messages passed using the IxNpeMh interface

•Direct data structure exchanges between the IxEthDB access-layer component and NPEs

The messages passed to/from the NPE and Intel XScale core are transferred via the IxNpeMh interface. Messages are written in the native endianness (BE or LE) and swapped independently by the Message Handler, before sending them to the NPEs. As mentioned in “NPE Message Handler

— IxNpeMh” on page 356, messages may contain multiple word-wide data elements.

IxEthDB does not explicitly swap data when communicating with the NPEs. Data structures directly exchanged by EthDB with the NPEs, such as trees and arrays with MAC addresses and additional information, are written in a byte-oriented manner, which guarantees correct operation when the memory is accessed in Big-Endian or Data Coherent Little-Endian mode. Tree uploads are handled identically, using byte accesses.

27.5.3.4.4Ethernet Access MIB Statistics

The Ethernet NPEs maintain error statistics, accessible via the IxEthAcc API. The statistics are recovered from the NPE via an SDRAM buffer. The buffer will be populated from the NPEs in Big-Endian mode. As such, all words undergo a Big-Endian-to-Little-Endian (Data Coherent) conversion before the results are returned to the user.

27.5.3.4.5Intel® IXP400 Software IxEthAcc and IxEthDB Summary

This section presents a summary of the changes that were made to the IxEthAcc component, assuming NPE is Big-Endian and all SDRAM is in Little-Endian Data Coherent mode.

April 2005	IXP400 Software Version 2.0	Programmer’s Guide
360	Document Number: 252539, Revision: 007