Intel® IXP400 Software
Access-Layer Components: Parity Error Notifier (IxParityENAcc) API
April 2005 IXP400 Software Version 2.0 Programmer’s Guide
236 Document Number: 252539, Revision: 007

16.2.2.7 Secondary Effects of Parity Interrupts

If the Intel XScale core detects an error on the AHB bus or on its private DDR memory interface
(MPI), an exception will be generated that will be serviced by its fault handler (such as data abort,
or prefetch abort exception handler). The MCU will also generate a parity interrupt in this case.
Caution: There is no guarantee as to the arrival order at the Intel XScale core of the data abort notification
versus the parity interrupt. The client application should respond accordingly. For guidance in
resolving the race condition between the data abort and the interrupt, refer to the scenarios
described in “Parity Error Notification Detailed Scenarios” on page 242.
The AHB-AHB bridge unit, upon receiving an “AHB Error” from the South AHB caused by a
parity error from a South AHB device, will respond with an AHB error to the originating master
(an NPE) on the North AHB. The AHB Coprocessor in the NPE will abort the transaction and
assert an error condition to the NPE, which will cause the NPE to lock up. This will result in an
NPE external coprocessor interrupt event to the Intel XScale core, as described in “Network
Processing Engines” on page234.
An NPE will report an ‘external’ error in the situation described above even though the chain of
events started with a parity error on a South AHB device (such as an AQM, Expansion Bus
Controller).
16.2.3 Interrupt Prioritization
Tabl e 45 shows the list of interrupts that the Intel XScale core would receive in the event of a parity
error. IxParityENAcc applies only the software defined priority as indicated; the top priority being
the priority 0 of the MCU.
Table 45. Parity Error Interrupts
Interrupt Bit1Default Priority2Software
Defined
Priority3Source Description
Int0 0 1 NPE-A IMEM, DMEM or External Errors
Int1 1 2 NPE-B IMEM, DMEM or External Errors4
Int2 2 3 NPE-C IMEM, DMEM or External Errors
Int8 8 6 PCI PCI Interrupt5
Int58 58 4 SWCP Switching Coprocessor Interrupt 4
Int60 60 5 AQM AHB Queue Manager Interrupt
Int61 61 0 MCU Single or Multi-Bit ECC Error. Multi-bit is
serviced first in IxParityENAcc.
Int62 62 7 EXP Expansion Bus Parity Error
NOTES:
1. Interrupts 32-61 are higher-priority (error class) interrupts than 0-31. For example, MCU interrupt will take priority over
NPE…even though the “Default Priority” table suggests otherwise.
2. The interrupt controller applies the default priorities and accordingly asserts the parity error interrupts to the Intel XScale
core.
3. The software defined priority is implemented by the access layer and is predefined.
4. A SWCP interrupt is also seen as an NPE-B external interrupt.
5. PCI Interrupts are those generated by the PCI Interrupt controller, and not the PCI Interrupt lines A,B,C and D.