Intel® IXP400 Software
Contents
Programmer’s Guide IXP400 Software Version 2.0 April 2005
Document Number: 252539, Revision: 007
15 Access-Layer Components:
NPE Message Handler (IxNpeMh) API............. ........................................................................ 225
15.1 What’s New...................................................................................... .................................225
15.2 Overview...................................................... .....................................................................225
15.3 Initializing the IxNpeMh....................................................................................... ..............226
15.3.1 Interrupt-Driven Operation........ ........................................................................... 226
15.3.2 Polled Operation....................... ........................................................................... 226
15.4 Uninitializing IxNpeMh ......................................................................................................227
15.5 Sending Messages from an Intel XScale® Core Software Client to an NPE ....................227
15.5.1 Sending an NPE Message.................................................................................. .227
15.5.2 Sending an NPE Message with Response............ ..............................................228
15.6 Receiving Unsolicited Messages from an NPE to Client Software..................... ..............229
15.7 Dependencies..................................................... .............................................................. 231
15.8 Error Handling........................................................................................ ...........................231
16 Access-Layer Components:
Parity Error Notifier (IxParityENAcc) API ........................................................ ........................233
16.1 What’s New...................................................................................... .................................233
16.2 Introduction........................ ............................................................................................... 233
16.2.1 Background.................................................................................. ........................233
16.2.2 Parity and ECC Capabilities in the
Intel® IXP45X and Intel® IXP46X Product Line ................................................... 234
16.2.2.1 Network Processing Engines................................. ..............................234
16.2.2.2 Switching Coprocessor in NPE B (SWCP) .......................................... 235
16.2.2.3 AHB Queue Manager (AQM).............................................. .................235
16.2.2.4 DDR SDRAM Memory Controller Unit (MCU)...................................... 235
16.2.2.5 Expansion Bus Controller ....................................................................235
16.2.2.6 PCI Controller ...................................................................................... 235
16.2.2.7 Secondary Effects of Parity Interrupts .................................................236
16.2.3 Interrupt Prioritization............................................................................. ..............236
16.3 IxParityENAcc API Details................. .... ... ... ... .... ... ... ... .....................................................237
16.3.1 Features.................................................................................... ...........................237
16.3.2 Dependencies.............................................. ........................................................237
16.4 IxParityENAcc API Usage Scenarios............................................................................... .238
16.4.1 Summary Parity Error Notification Scenario ........................................................ 239
16.4.2 Summary Parity Error Recovery Scenario................................... ........................241
16.4.3 Summary Parity Error Prevention Scenario.............................................. ...........242
16.4.4 Parity Error Notification Detailed Scenarios......................................................... 242
17 Access-Layer Components:
Performance Profiling (IxPerfProfAcc) API............................................................................. 247
17.1 What’s New...................................................................................... .................................247
17.2 Overview...................................................... .....................................................................247
17.3 Intel XScale® Core PMU.............................................................. .....................................248
17.3.1 Counter Buffer Overflow ...................................................................................... 249
17.4 Internal Bus PMU.......................................................................................... ....................249
17.5 Idle-Cycle Counter Utilities (‘Xcycle’).................................................. ..............................250
17.6 Dependencies..................................................... ..............................................................2 50
17.7 Error Handling........................................................................................ ...........................251
17.8 Interrupt Handling . .... ........................................................................................................ 251