Intel® IXP400 Software

 

 

 

 

Contents

 

27.4.3

Silicon Endianness Controls

349

 

 

27.4.3.1

Hardware Switches

349

 

 

27.4.3.2 Intel XScale® Core Endianness Mode

350

 

 

27.4.3.3 Little-Endian Data Coherence Enable/Disable

351

 

 

27.4.3.4

MMU P-Attribute Bit

351

 

 

27.4.3.5

PCI Bus Swap

352

 

 

27.4.3.6 Summary of Silicon Controls

352

 

27.4.4

Silicon Versions

352

 

27.5 Little-Endian Strategy in Intel® IXP400 Software and Associated BSPs

353

 

27.5.1

APB Peripherals

354

 

27.5.2

AHB Memory-Mapped Registers

355

 

27.5.3 Intel® IXP400 Software Core Components

355

 

 

27.5.3.1 Queue Manager — IxQMgr

355

 

 

27.5.3.2 NPE Downloader — IxNpeDl

356

 

 

27.5.3.3 NPE Message Handler — IxNpeMh

356

 

 

27.5.3.4 Ethernet Access Component — IxEthAcc

356

 

 

27.5.3.5

ATM and HSS

361

 

27.5.4

PCI

361

 

27.5.5 Intel® IXP400 Software OS Abstraction

361

 

27.5.6

VxWorks* Considerations

362

 

27.5.7

Software Versions

364

Figures

 

 

 

1

Intel® IXP400 Software v2.0 Architecture Block Diagram

28

2

Global Dependencies

33

3

Intel® IXP400 Software Buffer Flow

36

4

IXP_BUF User Interface

37

5

IXP_BUF Structure

38

6

OSAL IXP_BUF structure and macros

39

7

API User Interface to IXP_BUF

40

8

Access-Layer Component Interface to IXP_BUF

40

9

Pool Management Fields

41

10

IXP_BUF: IX_MBUF Structure

41

11

IXP_BUF: ix_ctrl Structure

42

12

IXP_BUF: NPE Shared Structure

43

13

Internal Mapping of IX_MBUF to the Shared NPE Structure

44

14

Buffer Transmission for a Scheduled Port

58

15

IxAtmdAccScheduleTable Structure and Order Of ATM Cell

60

16

Tx Done Recycling — Using a Threshold Level

61

17

Tx Done Recycling — Using a Polling Mechanism

62

18

Tx Disconnect

63

19

Rx Using a Threshold Level

65

20

RX Using a Polling Mechanism

66

21

Rx Disconnect

67

22

Services Provided by Ixatmm

74

23

Configuration of Traffic Control Mechanism

76

24

Component Dependencies of IxAtmm

77

25

Multiple VCs for Each Port, Multiplexed onto Single Line by the ATM Scheduler

82

26

Translation of IxAtmScheduleTable Structure to ATM Tx Cell Ordering

83

Programmer’s Guide

IXP400 Software Version 2.0

April 2005

 

 

 

Document Number: 252539, Revision: 007

 

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Intel IXP400 manual Figures