Intel IXP400 manual Document Number 252539, Revision

Intel® IXP400 Software

Endianness in Intel® IXP400 Software

#define htonl(A) (A) #define ntohs(A) (A) #define ntohl(A) (A)

#elif defined(LITTLE_ENDIAN) /* the value of A will be byte swapped */

#define htons(A) ((((A) & 0xff00) >> 8) ((A) & 0x00ff) << 8))

#define htonl(A) ((((A) & 0xff000000) >> 24) \

(((A) & 0x00ff0000) >> 8) \

(((A) & 0x0000ff00) << 8) \

(((A) & 0x000000ff) << 24))

#define ntohs htons #define ntohl htohl

#else

#error "One of BIG_ENDIAN or LITTLE_ENDIAN must be #defined."

#endif

27.4Endianness Features of the Intel® IXP4XX Product Line of Network Processors and IXC1100 Control Plane Processor

Within the Intel® IXP4XX Product Line of Network Processors and IXC1100 Control Plane Processors, there are several devices connected via the system bus. The system consists of the Intel XScale® Core, network processing engines, PCI devices, APB peripherals and expansion bus peripherals. The Intel XScale core may operate in either Little- or Big-Endian mode. The operation of the Intel XScale core in Little-Endian mode creates a mixed-endian system.

Supporting more than one endian in a system may have two meanings:

•Case 1: Either Big or Little-endian in the entire system, but not mixed;

•Case 2: Some hardware components running in one endian mode while others running in the other endian mode.

The IDEAL_BI_ENDIAN objectives cannot be achieved in the second case but can be achieved in the first case, as explained in “Endianness When Memory is Shared” on page 342. An IXP4XX processor or a system based upon such as processor belongs in the second case.

In order to support more than one endianness as implied by “Case 2”, a hardware byte-swapping or address swizzling (or munging) facility is usually employed.

When a piece of memory is accessed by different pieces of hardware through different buses, a bus bridge is usually a good place to perform byte swapping or address swizzling. This ensures that each processor does not need to do any endian adjustments. Instead, the processor assumes the underlying hardware behaves as if it is the same endianness as the processor.

April 2005	IXP400 Software Version 2.0	Programmer’s Guide
346	Document Number: 252539, Revision: 007