Intel IXP400 manual Data Flow in Channelized Service, HSS Packetized Transmit Buffering

Intel® IXP400 Software

Access-Layer Components: HSS-Access (IxHssAcc) API

Figure 68. HSS Packetized Transmit Buffering

IXP_BUFs

HssPacketizedTx0 -

HssPacketizedTx3

queues1. Descriptor read from packet- pipe-specific, Tx queue

2.Data (HDLC frame or RAW block) for each packet-pipe read

from appropriate mbuf, specified by descriptor

NPE-A	3. HDLC frame processing
Hss Packetized Tx	performed on each
Operation	packet-pipe configured
	for HDLC mode

HssPacketizedTxDone

queue

5. Descriptor returned	4. Data transmitted
when entire frame/	to HSS port
block sent.

		Frame 0					Frame 1			...
F0-	F0-	F0-	...	F0-	F1-	F1-	F1-	...	F1-
TSa	TSb	TSc		TSz	TSa	TSb	TSc		TSz

HSS Port Serial Data Stream

(TSa, TSb, ... = timeslots configured as "HDLC")

B2383-03

13.7.2Data Flow in Channelized Service

Data in the time slots configured as Voice64K/Voice56K types will be provided to the client via the IxHssAcc channelized service. There are up to 32 such channels per HSS port. The channelized service uses memory that is shared between the Intel XScale core and the NPEs. The client is responsible for allocating the memory for IxHssAcc to transmit and receive data through the HSS port.

For receive, ixOsServCacheDmaAlloc() of the IxOSCacheMMU component can be used to create a pointer to a pool of contiguous memory from the shared memory of the Intel XScale core and the NPEs. The pointer to this Rx data pool needs to be a physical address because NPE will directly write data into this memory area. The memory pool is divided into N circular buffers, one buffer per channel. N is the total number of channels in service.

April 2005	IXP400 Software Version 2.0	Programmer’s Guide
214	Document Number: 252539, Revision: 007