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Jameco Electronics 2000, 3000 manual 17.PWM LSB x Register, 18.PWM MSB x Register

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Table 7-17. PWM LSB x Register

n=255, normal

n=255, spread

n=256, spread

n=257, spread

n=258, spread

n=259, spread

n=259, normal

(64 counts)

(65 counts)

(65 counts)

(65 counts)

(65 counts)

(256 counts)

	(64		counts)			(64		counts)			(64		counts)

	(64		counts)			(64		counts)			(64		counts)
	(64		counts)			(64		counts)			(64		counts)


	(64		counts)				(65		counts)		(64		counts)


		(65		counts)			(65		counts)		(64		counts)


		(65		counts)			(65		counts)			(65 counts)

(260 counts)

Table 7-17. PWM LSB x Register

	PWM LSB x Register		(PWL0R)	(Address = 0x88)
			(PWL1R)	(Address = 0x8A)
			(PWL2R)	(Address = 0x8C)
			(PWL3R)	(Address = 0x8E)
Bit(s)	Value		Description

7:6	write	The least significant two bits for the Pulse Width Modulator count are stored.

5:1		These bits are ignored.

0	0	PWM output High for single block.

	1	Spread PWM output throughout the cycle.

Table 7-18. PWM MSB x Register

	PWM MSB x Register		(PWM0R)	(Address = 0x89)
			(PWM1R)	(Address = 0x8B)
			(PWM2R)	(Address = 0x8D)
			(PWM3R)	(Address = 0x8F)
Bit(s)	Value		Description

		The most significant eight bits for the Pulse Width Modulator count are stored.
7:0	write	With a count of "n", the PWM output will be High for "n + 1" clocks out of the
		1024 clocks of the PWM counter.

104	Rabbit 3000 Microprocessor

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Jameco Electronics 2000, 3000 manual 17.PWM LSB x Register, 18.PWM MSB x Register

Contents

Distributed by User’s Manual Rabbit 3000 MicroprocessorRabbit 3000 Microprocessor User’s Manual TrademarksRabbit Semiconductor Chapter 1. Introduction TABLE OF CONTENTSChapter 2. Rabbit 3000 Design Features Chapter 4. Rabbit Capabilities Parallel Ports Chapter 14. Rabbit 3000 Clocks Appendix A. The Rabbit Programming Port Rabbit 3000 Microprocessor User’s Manual 1. INTRODUCTIONRabbit 3000 Microprocessor 1.1 Features and Specifications RabbitUser’s Manual •There is a built-inwatchdog timer User’s Manual Figure 1-1.Rabbit 3000 Block Diagram1.2 Summary of Rabbit 3000 Advantages Feature 1.3 Differences Rabbit 3000 vs. RabbitRabbit RabbitRabbit FeatureRabbit Serial ports with support for SDLC/HDLC IrDAUser’s Manual 2.RABBIT 3000 DESIGN FEATURESRabbit 3000 Microprocessor 2.2.2 Serial Ports 2.2 Overview of On-ChipPeripherals and Features2.2.1 5 V Tolerant Inputs Rabbit 3000 Microprocessor 2.2.3 System Clock2.2.4 32.768 kHz Oscillator Input Figure 2-2.Digital Filtering Input Pins 2.2.5 Parallel I/OExternal Input Filtered InputRabbit 2.2.6 Slave Port2.2.7 Auxiliary I/O Bus 2.2.8 TimersFigure 2-4.Rabbit Timers A and B 2.2.9 Input Capture ChannelsUser’s Manual 2.2.10 Quadrature Encoder Inputs2.2.11 Pulse Width Modulation Outputs 2.3 Design Standards 2.2.13 Separate Core and I/O Power Pins2.2.12 Spread Spectrum Clock 2.3.1 Programming Port2.4 Dynamic C Support for the Rabbit 2.3.2 Standard BIOSRabbit 3000 Microprocessor 3.1Processor Registers 3.DETAILS ON RABBIT MICROPROCESSOR FEATURESRabbit 3000 Microprocessor 3.2 Memory Mapping Figure 3-3.Example of Memory Mapping Operation Figure 3-4 shows a memory interface unit Rabbit 3000 Microprocessor 3.2.1 Extended Code SpaceCompiler inserts Compiler notices thatcode has passed F000 long jump in codexpc window stack 3.2.3 Using the Stack Segment for Data Storage Data RAM Root Code 3.2.4 Practical Memory ConsiderationsData RAM Root Code User’s Manual 3.3 Instruction Set Outline User’s Manual 3.3.1 Load Immediate Data to a Register3.3.3 Load or Store Data Using an Index Register User’s Manual 3.3.4 Register-to-RegisterMove3.3.5 Register Exchanges 3.3.7 16-bitArithmetic and Logical Ops 3.3.6 Push and Pop InstructionsUser’s Manual extend sign of l to HL User’s Manual 3.3.8 Input/Output Instructions3.4.3 Manipulation of Boolean Variables 3.4.1 Zero HL in 4 Clocks3.4.2Exchanges Not Directly Implemented User’s Manual 3.4.4 Comparisons of Integerstest for 3.4.5 Atomic Moves from Memory to I/O Space 3.5.1 Interrupt Priority 3.5 Interrupt StructureProcessor IPSET 1, IPSET 2, IPSETPriority Effect on InterruptsLD SP,HL IOI LD sseg,a 3.5.2 Multiple External Interrupting DevicesLD SP,HL LD SP,IY LD SP,IX 3.5.4 Critical Sections 3.5.5 Semaphores Using Bit B,HL3.5.6 Computed Long Calls and Jumps 4.1 Precisely Timed Output Pulses 4.RABBIT CAPABILITIESRabbit 2000 Microprocessor 4.2 Open-DrainOutputs Used for Key Scan Rabbit 2000 Microprocessor 4.3 Cold BootUser’s Manual 4.4 The Slave PortRabbit 2000 Microprocessor 4.4.1 Slave Rabbit As A Protocol UARTUser’s Manual 5.PIN ASSIGNMENTS AND FUNCTIONSRabbit 3000 Microprocessor 5.1 LQFP Package5.1.1 Pinout 16.00 ± 0.25 mm 5.1.2 Mechanical Dimensions and Land Pattern14.00 ± 0.10 mm 14.00 ± 0.10 mmToe Fillet TOLERANCE AND SOLDER JOINT ANALYSISHeel Fillet Side Fillet5.2.1 Pinout 5.2 Ball Grid Array PackageA B C D E F G H J K L M User’s ManualTable 5-2.Ball and Land Size Dimensions 5.2.2 Mechanical Dimensions and Land Patternall dimensions in mm Table 5-3.Design ConsiderationsUser’s Manual Figure 5-5.BGA Package OutlineTOP VIEW BOTTOM VIEWTable 5-1.Rabbit Pin Descriptions 5.3 Rabbit Pin DescriptionsTable 5-1.Rabbit Pin Descriptions continued Figure 5-6.Bus Timing Read and Write 5.4 Bus TimingTable 5-2.Pins With Alternate Functions 5.5 Description of Pins with Alternate FunctionsTable 5-2.Pins With Alternate Functions continued Table 5-3.Parallel Port x Alternate Functions Table 5-5.Rabbit 3000 Absolute Maximum Ratings 5.6 DC CharacteristicsTable 5-6.3.3 Volt DC Characteristics User’s Manual 5.7 I/O Buffer Sourcing and Sinking LimitRabbit 3000 Microprocessor User’s Manual 6.RABBIT INTERNAL I/O REGISTERSISR Starting Address On-ChipPeripheralTable 6-2.Rabbit Internal I/O Registers ResetRegister Name MnemonicTable 6-2.Rabbit Internal I/O Registers continued Port E Bit 7 Register Table 6-2.Rabbit Internal I/O Registers continuedPWM MSB 0 Register Table 6-2.Rabbit Internal I/O Registers continuedTable 6-2.Rabbit Internal I/O Registers continued Timer A Time Constant 5 RegisterSerial Port D Address Register Table 6-2.Rabbit Internal I/O Registers continued7.1Processor Identification 7.MISCELLANEOUS FUNCTIONSMain Clock 7.2 Rabbit Oscillators and Clocks32.768 kHz Clock RabbitTable 7-6.Clock Select Field of GCSR Table 7-5.Global Control/Status RegisterTable 7-7.Global Clock Double Register 7.3 Clock DoublerOscillator Oscillator delayed and inverted User’s Manual 7.4 Clock Spectrum Spreader User’s Manual 7.5 Chip Select Options for Low PowerGPSCR Global Power Save Control RegisterAddress = 0x0D Bits32 kHz Figure 7-4.Short Chip Select Memory ReadADDR Valid7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN User’s Manual 7.7 Time/Date Clock Real-TimeClockTable 7-10. Real-TimeClock RTCxR Data Registers 7.8 Watchdog Timer 0x51 User’s Manual 7.9 System ResetPost-Reset† RESET LowPin Name Direction7.10 Rabbit Interrupt Structure Action Required to Clear the Interrupt PriorityInterrupt Source 7.10.1 External Interrupts Reg Address Reg NameBits 7,6 Bits 5,4User’s Manual 7.11 Bootstrap OperationRabbit 3000 Microprocessor 7.12 Pulse Width Modulator Table 7-18.PWM MSB x Register Table 7-17.PWM LSB x RegisterTimer A8 7.13 Input CaptureCPT input InterruptRabbit 3000 Microprocessor Input Capture Control/Status Register Table 7-19.Input Capture Control/Status RegisterICCSR Address =Table 7-21.Input Capture Trigger x Register Table 7-20.Input Capture Control RegisterTable 7-24.Input Capture MSB x Register Table 7-22.Input Capture Source x RegisterTable 7-23.Input Capture LSB x Register I input 7.14 Quadrature DecoderQ input Counter 00User’s Manual RejectedAccepted QDCSR Quad Decode Control/Status RegisterAddress = BitsTable 7-27.Quadrature Decoder Count Register Table 7-26.Quadrature Decoder Control RegisterRabbit 3000 Microprocessor 8.1Interface for Static Memory Chips 8.MEMORY INTERFACE AND MAPPINGFigure 8-2.Typical Memory Chip Connection Rabbit8.3 Memory-MappingUnit 8.2 Memory Mapping OverviewProcessor Memory Mapping UnitPage User’s Manual 8.4 Memory Interface Unit8.5 Memory Bank Control Registers MMU Instruction/Data Register Table 8-4.MMU Instruction/Data Register MMIDR =MMIDR Address =Table 8-5.MMU Expanded Code Register MECR = Breakpoint/Debug Control Register 8.6 Allocation of Extended Code and DataBDCR Address = 0x01CBits 7:5 8.7 Instruction and Data Space SupportCombined I & D 64k+4*n User’s Manual 8.8 How the Compiler Compiles to MemoryRabbit 3000 Microprocessor 9. PARALLEL PORTS 9.1 Parallel Port A 9.2 Parallel Port B Table 9-6.Parallel Port C Register Bit Functions 9.3 Parallel Port CTable 9-5.Parallel Port C Registers Table 9-7.Parallel Port D Registers 9.4 Parallel Port DPD3 PD0 perclk/2 Timer A1 Timer B1 Timer B2 perclk/2 Timer A1 Timer B1 Timer B2Figure 9-1.Parallel Port D Block Diagram I/O DataTable 9-9.Parallel Port D Control Register adr = Table 9-8.Parallel Port D Register functions•PDDR—ParallelPort D data register. Read/Write 9.5 Parallel Port E Rabbit 3000 Microprocessor Table 9-10.Parallel Port E RegistersTable 9-12.Parallel Port E Control Register adr = Table 9-11.Parallel Port E Register functionsTable 9-14.Parallel Port F Register Functions 9.6 Parallel Port FTable 9-13.Parallel Port F Registers User’s Manual 9.6.1 Using Parallel Port A and Parallel Port F• Full Functionality • Parallel Inputs• Parallel Outputs • Parallel Inputs, PWM, Serial Port ClocksTable 9-16.Parallel Port G Registers 9.7 Parallel Port GRabbit 3000 Microprocessor TableParallel Port G Control Register adr= 0x04C ADDR write data write strobe 10.I/O BANK CONTROL REGISTERST1 Tw T2 read data read strobe chip select strobeTable 10-1.I/O Bank x Control Register Port E Control RegisterI/O Address I/O AddressRabbit 3000 Microprocessor Figure 11-1.Block Diagram of Timers A and B 11. TIMERS11.1 Timer A 11.1.1 Timer A I/O Registers Table Timer A CapabilitiesTable 11-3.Timer A Control and Status Register A4 interrupt disabled Table 11-5.Timer A Prescale Register Table 11-4.Timer A Control RegisterUser’s Manual 11.1.2 Practical Use of Timer A11.2 Timer B Table 11-8.Timer B Control Register Table 11-7.Timer B Control and Status RegisterTable 11-10.Timer B Count LSB x Registers Table 11-9.Timer B Count MSB x RegistersTable 11-11.Timer B Count MSB Register Table 11-12.Timer B Count LSB Register11.2.1 Using Timer B Rabbit 3000 Microprocessor Table 12-1.Serial Port Signals 12.RABBIT SERIAL PORTSCLKA Timer A4 Serial Port A TXA User’s Manual 12.1 Serial Port Register Layout User’s Manual Table 12-2.Serial Port A Registers 12.2 Serial Port RegistersTable 12-3.Serial Port B Registers Table 12-4.Serial Port C RegistersTable 12-7.Serial Port F Registers Table 12-5.Serial Port D RegistersTable 12-6.Serial Port E Registers Table 12-9.Address Register All Ports Table 12-8.Data Register All PortsTable 12-10.Long Stop Register All Ports Serial Port x Status Register Serial Port x Status Register Serial Port x Status Register Description HDLC mode onlySESR Address = 0xCBSACR Serial Port x Control RegisterAddress = 0xC4 SBCRSCCR Serial Port x Control RegisterAddress = 0xE4 SDCRSECR Serial Port x Control RegisterAddress = 0xCC SFCRSerial Port x Extended Register Normal clocked serial operation Normal HDLC data encoding Request Interrupt 12.3 Serial Port InterruptTransmitter IRQ Rabbit 3000 Microprocessor 12.4 Transmit Serial Data Timing12.5 Receive Serial Data Timing 12.6 Clocked Serial Ports User’s Manual Rabbit 3000 Microprocessor 12.7.2 Clocked Serial Timing with External Clock 12.7 Clocked Serial Timing12.7.1 Clocked Serial Timing With Internal Clock CLKA perclkValid Rabbit 3000 MicroprocessorUser’s Manual 12.8 Synchronous Communications on Ports E and FValid Data Hits Last Byte Bit PatternUser’s Manual Rabbit 3000 Microprocessor User’s Manual 12.9 Serial Port Software Suggestions User’s Manual 12.9.1 Controlling an RS-485Driver and Receiver12.9.2 Transmitting Dummy Characters 12.9.3 Transmitting and Detecting a Break stop bit 7 12.9.9 Rabbit-OnlyMaster/Slave Protocol 12.9.8 Supporting 9th Bit Communication Protocols12.9.10 Data Framing/Modbus Rabbit 3000 MicroprocessorUser’s Manual Rabbit 3000 Microprocessor SD0-SD7 13.RABBIT SLAVE PORTSlave Port Write Cycle Slave Port Read CycleSA1, SA0 SRD SD7:0Parameter SymbolMinimum MaximumMaster writes SPD0R Master Rabbit ResetFirst Slave Rabbit D0–D7Table 13-1.Slave Port Registers 13.2 Slave Port RegistersThe functionality of the bits is as follows Table 13-3.Slave Port Status Register SPSR adr = 13.3.1 Slave ApplicationsUser’s Manual 13.3.2 Master-SlaveMessaging ProtocolRabbit 3000 Microprocessor Figure 14-1.Rabbit 3000 Main Oscillator Circuit 14.RABBIT 3000 CLOCKSRabbit 3000 Microprocessor 14.1 Low-PowerDesignUser’s Manual 15. EMI CONTROL15.2 Using the Clock Spectrum Spreader 15.1 Power Supply Connections and Board LayoutTable 15-2.Spread Spectrum Mode Select Rabbit 3000 Microprocessor 16.1 Memory Access Time 16.AC TIMING SPECIFICATIONSdelay CLK A19:0 CSx WEx D7:0D7:0 Tsetup•T = -40Cto 85C, V = 3.3 CLK A19:0 CSx WEx D7:0 D7:0Tsetup CLK A19:0Example Max. delay @ 2.5 V = 7.6 + 1.67n - Min. delay @ 3.3 V = 3.7 + 0.75n -Min. delay @ 2.5 V = 4.7 + 1.03n - Max. delay @ 1.8 V = 12.2 + 2.7n -•Clock = 29.49 MHz •T = 34 ns ExampleCLK A15:0 16.2 I/O Access TimeIOCSx IORDThe following I/O read time delays were measured User’s Manual 16.3 Further Discussion of Bus and Clock TimingOscillator Oscillator delayed and inverted 16.4 Maximum Clock Speeds Figure 16-8.External Oscillator Buffer +3.3 XTALA1User’s Manual 16.5 Power and Current Consumptionenlarged view over 0–16MHz range 32MHz and 1.4 µA at 2 kHz Rabbit 3000 Microprocessor 16.6 Current Consumption MechanismsItotal µA = 0.32 × V × f + 0.23 × Vc × f + 5 × Vc 16.7 Sleepy Mode Current Consumption16.8 Memory Current Consumption 16.9 Battery-BackedClock Current Consumption Design Recommendations 16.10 Reduced-PowerExternal Main Oscillator17.1.1 BIOS Services 17.RABBIT BIOS AND VIRTUAL DRIVER17.1 The BIOS 17.2.2 Watchdog Timer Support 17.1.2 BIOS Assumptions17.2 Virtual Driver 17.2.1 Periodic InterruptUser’s Manual Rabbit 3000 Microprocessor 18.OTHER RABBIT SOFTWARE 18.1Power Management Support18.2 Reading and Writing I/O Registers 18.2.1 Using Assembly Language18.2.2 Using Library Functions 18.3.2 Interrupt While Updating Registers 18.3 Shadow Registers18.3.1 Updating Shadow Registers 18.3.2.2 Non-atomicInstructions 18.4 Timer and Clock UsageThe format of the structure used is the following Rabbit 3000 Microprocessor Summary 19.RABBIT INSTRUCTIONSALTD “A” Column Symbol Key Spreadsheet ConventionsIOI and IOE “I” Column Symbol Key Flag Register KeyRabbit SymbolsZ180 Meaning19.2 Load & Store to Immediate Address 19.1 Load Immediate Data19.3 8-bitIndexed Load and Store 19.4 16-bitIndexed Loads and StoresUser’s Manual 19.5 16-bitLoad and Store 20-bitAddress19.6 Register to Register Moves 19.9 16-bitArithmetic and Logical Ops 19.7 Exchange Instructions19.8 Stack Manipulation Instructions User’s Manual 19.10 8-bitArithmetic and Logical Ops19.12 8-bitIncrement and Decrement 19.118-bitBit Set, Reset and TestUser’s Manual 19.13 8-bitFast A Register Operations19.14 8-bitShifts and Rotates 19.16 Block Move Instructions 19.15 Instruction PrefixesUser’s Manual 19.17 Control Instructions - Jumps and Calls19.18 Miscellaneous Instructions 19.19 Privileged Instructions 20.DIFFERENCES RABBIT VS. Z80/Z180 INSTRUCTIONS Rabbit Instructions to Use Z80/Z180 Instructions DroppedIOI and IOE “I” Column Symbol Key ALTD “A” Column Symbol KeySpreadsheet Conventions Flag Register KeyBit select SymbolsInstruction Instruction Instruction Instruction Instruction Rabbit 3000 Microprocessor PROGRAMMING PORT PIN ASSIGNMENTS APPENDIX A. THE RABBIT PROGRAMMING PORTRabbit LQFP pins are shown in parenthesis Rabbit 3000 Microprocessor A.2 Alternate Programming Port•doubler in use 52/48 duty cycle, and A.3 Suggested Rabbit Crystal Frequencies•spectrum spreader set to normal Table A-1.Preliminary Crystal Frequencies Memory Access Times, and Baud RatesUser’s Manual APPENDIX B. RABBIT 3000 REVISIONSRabbit 3000 Microprocessor User’s Manual Rabbit B.1 Discussion of Fixes and ImprovementsRabbit DescriptionReset B.1.1 Rabbit Internal I/O RegistersRegister Name MnemonicExternal Interrupt User Enable Register Global Power Save Control Register Table B-4.Rabbit 3000 I/O Address Ranges B.1.2 Peripheral and ISR Addressand Interrupt Service Vectors Table B-4.Rabbit 3000 I/O Address Ranges and Interrupt Service Vectors continued continuedProcessor Revision B.1.3 Revision-LevelID RegisterPackage GCPUUser’s Manual B.1.4 System/User ModeB.1.5 Memory Protection Write Protect Low Register Table B-7.Write Protect Low RegisterWPLR Address =Table B-9.Write Protect Segment x Register Table B-8.Write Protect High RegisterWrite Protect Segment x Low Register Table B-10.Write Protect Segment x Low RegisterWPSALR Address =Write Protect Segment x High Register Table B-11.Write Protect Segment x High RegisterWPSAHR Address =B.1.6 Stack Protection Table B-14.Stack High Limit Register Table B-12.Stack Limit Control RegisterTable B-13.Stack Low Limit Register Table B-15.RAM Segment Register B.1.7 RAM Segment RelocationTable B-17.Secondary Watchdog Timer Register B.1.8 Secondary Watchdog TimerLDDSR B.1.9 New OpcodesLDISR LSDRLDIR LDDRLSDR LSIRTable B-20.MMU Instruction/Data Register B.1.10 Expanded I/O Memory AddressingI/O Bank x Control Register B.1.11 External I/O ImprovementsTable B-21 Table B-22.Global Power Save Control Register B.1.12 Short Chip Select Timing for WritesTable B-24.Clock Select Field of GCSR Table B-23.Global Control/Status RegisterUser’s Manual B.1.12.2 Short Chip Select Timingo s c illa to r oscillator 32 kHz 32 kHz clock 32 kHzADDR ValidUser’s Manual oscillator oscillator 32KkHz User’s Manual 32 kHz Figure B-21.PWM Interrupt and Output Timing B.1.13 Pulse Width Modulator ImprovementsTable B-26.PWM LSB 1 Register Table B-25.PWM LSB 0 RegisterPWM LSB x Register Table B-27.PWM LSB 2 and 3 RegistersPWL2R Address = 0x008CTable B-29.Quadrature Decoder Count High Register B.1.14 Quadrature Decoder ImprovementsTable B-28.Quadrature Decoder Control Register I input User’s ManualQ input Cnt 8 bitB.2 Pins with Alternate Functions User Mode APPENDIX C. SYSTEM/USER MODESystem Mode C.1 System/User Mode Opcodes Table C-3.System/User Mode I/O Registers C.2 System/User Mode RegistersTable C-4.I/O Addresses Inaccessible in User Mode INTERRUPT UNDER USER CONTROL C.3 InterruptsINTERRUPT UNDER SYSTEM CONTROL Rabbit 3000 Microprocessor C.3.1 Peripheral Interrupt PrioritizationAction required to clear the interrupt PriorityInterrupt Source C.4.1 Memory Protection Only C.4 Using the System/User ModeUser’s Manual C.4.2 Mixed System/User Mode OperationSYSCALL C.4.3 Complete Operating SystemInterrupt Rabbit 3000A Internal I/O Registers APPENDIX D. RABBIT 3000A INTERNAL I/O REGISTERSTable D-1 Rabbit 3000 Microprocessor I/O Bank User Enable Register Port D Bit 2 Register I/O Bank 2 Control Register Interrupt 0 Control Register Serial Port B Address Register Rabbit 3000 Microprocessor User’s Manual NOTICE TO USERSPage Numerics INDEXPage TATxR