Jameco Electronics 3000, 2000 manual Auxiliary I/O Bus, Timers

2.2.7 Auxiliary I/O Bus

The Rabbit 3000 instruction set supports memory access and I/O access. Memory access takes place in a 1 megabyte memory space. I/O access takes place in a 64K I/O space. In a traditional microprocessor design the same address and data lines are used for both mem- ory and I/O spaces. Sharing address and data lines in this manner often forces compromises or makes design more complicated. Generally the memory bus has more critical timing and less tolerant of additional capacitive loading imposed by sharing it with an I/O bus.

With the Rabbit 3000, the designer has the option of enabling completely separate buses for I/O and memory. The auxiliary I/O bus uses many of the same pins used by the slave port, so its operation is mutually exclusive from operation of the slave port. Parallel Port A is used to provide 8 bidirectional data lines. Parallel Port B bits 2:7 provide 6 address lines, the least significant 6 lines of the 16 lines that define the full I/O space. The auxil- iary bus is only active on I/O bus cycles. The address lines remain in the same state assumed at the end of the previous I/O cycle until another I/O cycle takes place. I/O chip selects as well as read and write strobes are available at various other pins so that the 64 byte space defined by the 6 address lines may be easily expanded. I/O cycles also execute in parallel on the main (memory) bus when they take place on the auxiliary bus, so addi- tional address lines can be buffered and provided if needed.

By connecting I/O devices to the auxiliary bus, the fast memory bus is relieved of the capacitive load that would otherwise slow the memory. For core modules based on the Rabbit 3000, fewer pins are required to exit the core module since the slave port and the I/O bus can share the same pins and the memory bus no longer needs to exit the module to provide I/O capability. Because the I/O bus has less activity and is slower than the memory bus, it can be run further physically without EMI and ground bounce problems. 5 V signals can appear on the I/O bus since the Rabbit 3000 inputs are 5 V tolerant. 5 V signals could easily cause problems on the main bus if non 5 V tolerant 3.3 V memories are connected.

2.2.8 Timers

The Rabbit has several timer systems. The periodic interrupt is driven by the 32.768 kHz oscillator divided by 16, giving an interrupt every 488 µs if enabled. This is intended to be used as a general-purpose clock interrupt. Timer A consists of ten 8-bit countdown and reload registers that can be cascaded up to two levels deep. Each countdown register can be set to divide by any number between 1 and 256. The output of six of the timers is used to provide baud clocks for the serial ports. Any of these registers can also cause interrupts and clock the timer-synchronized parallel output ports. Timer B consists of a 10-bit counter that can be read but not written. There are two 10-bit match registers and comparators. If the match register matches the counter, a pulse is output. Thus the timer can be programmed to output a pulse at a predetermined count in the future. This pulse can be used to clock the timer-synchronized parallel-port output registers as well as cause an interrupt. Timer B is convenient for creating an event at a precise time in the future under program control.

Figure 2-4illustrates the Rabbit timers.

User’s Manual 15