Jameco Electronics 3000, 2000 manual Further Discussion of Bus and Clock Timing, User’s Manual

16.3 Further Discussion of Bus and Clock Timing

The clock doubler is normally used, except in situations where low-frequency systems are specifically being used. The clock doubler works by oring the clock with a delayed ver- sion of itself. The nominal delay varies from 6 to 20 ns, and is settable under program con- trol. Any asymmetry in the oscillator waveform before it is doubled will result in alternate clocks having slightly different periods. Using the suggested oscillator circuit, the asym- metry is no worse than 52%–48%. This results in a given clock being shortened by the ratio 50/52, or 4%. Memory access time is not affected because memory bus cycle is 2 clocks long and includes both a long and a short clock, resulting in no net change due to asymmetry. However, if an odd number of wait states is used, then the memory access time will be affected slightly.

When the clock spectrum spreader is enabled, clock periods are shortened by a small amount depending on whether the “normal” or the “strong” spreader setting is used, and depending on the operating voltage. If the clock doubler is used, the spectrum spreader affects every other cycle and reduces the clock high time. If the doubler is not used, then the spreader affects every clock cycle, and the clock low time is reduced. Of course, the spectrum spreader also lengthens clock cycles, but only the worst case shortening is rele- vant for calculating worst case access times. The numbers given for clock shortening with the doubler disabled are the combined shortening for 2 consecutive clock cycles, worst case.

In computing memory requirements, the important considerations are address access time, output enable access time, and minimum write pulse required. Increasing the clock dou- bler delay increases the output enable time, but decreases memory write pulse width. The early write pulse option can be used to ensure a long-enough write pulse, but then it must be ensured that the write pulse does not begin before the address lines have stabilized.

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