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Jameco Electronics 3000, 2000 manual Parallel Port E Register functions

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Table 9-11. Parallel Port E Register functions

		Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0

	PEDR (R/W)	PE7	PE6	PE5	PE4	PE3	PE2	PE1	PE0
	adr = 0x070	PE7	PE6	PE5	PE4	PE3	PE2	PE1	PE0
	adr = 0x070

	PEFR (W)	alt /I7	alt /I6	alt /I5	alt /I4	alt /I3	alt /I2	alt /I1	alt /I0
	adr = 0x075	alt /I7	alt /I6	alt /I5	alt /I4	alt /I3	alt /I2	alt /I1	alt /I0
	adr = 0x075

	PEDDR (W)	dir =	dir =	dir =	dir =	dir =	dir =	dir =	dir =
	adr = 0x077	out	out	out	out	out	out	out	out

	PEB0R (W)	x	x	x	x	x	x	x	PE0
	adr = 0x078	x	x	x	x	x	x	x	PE0
	adr = 0x078

	PEB1R (W)	x	x	x	x	x	x	PE1	x
	adr = 0x079	x	x	x	x	x	x	PE1	x
	adr = 0x079

	PEB2R (W)	x	x	x	x	x	PE2	x	x
	adr = 0x07A	x	x	x	x	x	PE2	x	x
	adr = 0x07A

	PEB3R (W)	x	x	x	x	PE3	x	x	x
	adr = 0x07B	x	x	x	x	PE3	x	x	x
	adr = 0x07B

	PEB4R (W)	x	x	x	PE4	x	x	x	x
	adr = 0x07C	x	x	x	PE4	x	x	x	x
	adr = 0x07C

	PEB5R (W)	x	x	PE5	x	x	x	x	x
	adr = 0x07D	x	x	PE5	x	x	x	x	x
	adr = 0x07D

	PEB6R (W)	x	PE6	x	x	x	x	x	x
	adr = 0x07E	x	PE6	x	x	x	x	x	x
	adr = 0x07E

	PEB7R (W)	PE7	x	x	x	x	x	x	x
	adr = 0x07F	PE7	x	x	x	x	x	x	x
	adr = 0x07F

Table 9-12. Parallel Port E Control Register (adr = 0x074)

	Bits 7, 6	Bits 5, 4	Bits 3, 2	Bits 1, 0

		00—clock upper nibble on pclk/2		00—clock lower nibble on pclk/2
	x,x	01—clock on timer A1	x,x	01—clock on timer A1
	x,x	10—clock on timer B1	x,x	10—clock on timer B1
		10—clock on timer B1		10—clock on timer B1
		11—clock on timer B2		11—clock on timer B2

User’s Manual

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Jameco Electronics 3000, 2000 manual Parallel Port E Register functions, Parallel Port E Control Register adr =

Contents

Page Rabbit 3000 Microprocessor Trademarks Rabbit SemiconductorTable of Contents Rabbit Internal I/O Registers Parallel Ports 129 Rabbit 3000 Clocks 209 Appendix B. Rabbit 3000 Revisions 273 Rabbit 3000 Microprocessor Introduction Features and Specifications Rabbit User’s Manual 1shows a block diagram of the Rabbit CPU Summary of Rabbit 3000 Advantages Feature Rabbit Differences Rabbit 3000 vs. RabbitSerial ports with support for SDLC/HDLC IrDA Rabbit 3000 Design Features Rabbit 8-bit Processor vs. Other Processors 1 5 V Tolerant Inputs Overview of On-Chip Peripherals and FeaturesSerial Ports System Clock 4 32.768 kHz Oscillator InputParallel I/O Cascaded Output Registers for Parallel Ports D and ESlave Port RabbitTimers Auxiliary I/O BusInput Capture Channels PWMQuadrature Encoder Inputs Pulse Width Modulation OutputsSeparate Core and I/O Power Pins Design StandardsSpread Spectrum Clock Programming PortStandard Bios Dynamic C Support for the RabbitRabbit 3000 Microprocessor Details on Rabbit Microprocessor Features Processor RegistersRabbit 3000 Microprocessor Memory Mapping Addressing Memory ComponentsExample of Memory Mapping Operation 4shows a memory interface unit Extended Code Space Separate I and D Space Extending Data Memory Use of XPC SegmentXpc window stack Using the Stack Segment for Data Storage Practical Memory Considerations Data RAM Root CodeUser’s Manual Instruction Set Outline Load Immediate Data to a Register Load or Store Data from or to a Constant AddressLoad or Store Data Using an Index Register Other 8-bit loads and stores are the followingRegister-to-Register Move Register ExchangesPush and Pop Instructions 7 16-bit Arithmetic and Logical OpsBool SBC instruction can also be used to perform a sign extension Input/Output Instructions How to Do It in Assembly Language-Tips and Tricks Zero HL in 4 ClocksExchanges Not Directly Implemented Manipulation of Boolean VariablesComparisons of Integers HLB Atomic Moves from Memory to I/O Space Interrupt Structure Interrupt PriorityEffect of Processor Priorities on Interrupts Processor Priority Effect on InterruptsMultiple External Interrupting Devices Privileged Instructions, Critical Sections and SemaphoresSemaphores Using Bit B,HL Critical SectionsComputed Long Calls and Jumps Rabbit Capabilities Precisely Timed Output PulsesPulse Width Modulation to Reduce Relay Power Using Open-Drain Outputs for Key Scan Open-Drain Outputs Used for Key ScanCold Boot Slave Port Slave Rabbit As a Protocol Uart PIN Assignments and Functions Lqfp Package PinoutMechanical Dimensions and Land Pattern Same pin dimensions apply along the x axis and the y axisPC Board Land Pattern for Rabbit 3000 128-pin Lqfp C D E F G H J K L M Ball Grid Array PackageBall and Land Size Dimensions Design Considerations All dimensions in mmKey Feature Recommendation Nominal Ball Tolerance Ball Pitch Nominal LandBGA Package Outline Rabbit Pin Descriptions Rabbit Pin DescriptionsPin Pin Group Pin Name Direction Function Numbers Lqfp TfbgaVddcore Bus Timing Bus Timing Read and WriteDescription of Pins with Alternate Functions Pins With Alternate FunctionsPF7 PWM3 AQD2A Parallel Port x Alternate Functions Parallel Port x Alternate Functions Control BitsDC Characteristics 3 Volt DC CharacteristicsSymbol Parameter Maximum Rating Symbol Parameter Test Conditions Min Typ Max UnitsI/O Buffer Sourcing and Sinking Limit Rabbit 3000 Microprocessor Rabbit Internal I/O Registers Rabbit 3000 Peripherals and Interrupt Service Vectors On-Chip Peripheral ISR Starting AddressRegister Name Mnemonic Address Reset Default Values for all the Peripheral Control RegistersRabbit Internal I/O Registers Grev PEB7R PWM0R Tbcsr Sdar Global ROM Configuration Register Global RAM Configuration RegisterMiscellaneous Functions Processor IdentificationRabbit Oscillators and Clocks Global CPU RegisterGlobal Revision Register GcpuRabbit Global Control/Status Register Clock Select Field of GcsrGlobal Control/Status Register GcsrRecommended Delays Set In Gcdr for Clock Doubler Clock DoublerGlobal Clock Double Register GcdrEffect of Clock Doubler User’s Manual Clock Spectrum Spreader Reduction in Peak Spectral Strength from Spectrum SpreaderChip Select Options for Low Power Global Power Save Control Register Address = 0x0DShort Chip Select Memory Read Output Pins CLK, STATUS, /WDTOUT, /BUFEN Global Output Control Register Gocr = 0x0ETime/Date Clock Real-Time Clock 10. Real-Time Clock RTCxR Data Registers 11. Real-Time Clock Control Register Rtccr adr =Watchdog Timer 12. Watchdog Timer Control Register Wdtcr adr =13. Watchdog Timer Test Register Wdttr adr = System Reset 14. Rabbit 3000 Reset Sequence and State of I/O Pins Pin Name Direction Reset Low Post-Reset† Recognized by CPURabbit Interrupt Structure 15. Interrupts-Priority and Action to Clear Requests External Interrupts External Interrupt Line Logic16. Control Registers for External Interrupts Interrupt Vectors INT0 EIR,0x00/INT1 EIR,0x08Reg Name Reg Address Bits 7,6 Bits 5,4 Bits 3,2 Bits 1,0 Bootstrap Operation 102 Rabbit 3000 Microprocessor Pulse Width Modulator Pulse Width LSBs 1st 2nd 3rd 4th17. PWM LSB x Register 18. PWM MSB x RegisterInput Capture 106 Rabbit 3000 Microprocessor Input Capture Control/Status Register 19. Input Capture Control/Status RegisterIccsr 20. Input Capture Control Register 21. Input Capture Trigger x RegisterIccr ICT1R23. Input Capture LSB x Register 22. Input Capture Source x Register24. Input Capture MSB x Register Quadrature Decoder Rejected Quad Decode Control/Status Register 25. Quadrature Decoder Control/Status RegisterQdcsr 26. Quadrature Decoder Control Register 27. Quadrature Decoder Count RegisterQdcr QDC1R114 Rabbit 3000 Microprocessor Memory Interface and Mapping Interface for Static Memory ChipsData Lines Static Address Lines Memory Flash RabbitRAM Memory-Mapping Unit Memory Mapping OverviewProcessor Memory Mapping Unit Interface Memory Chips 64K Segment RegistersSegment Size Register Segment Register FunctionMemory Interface Unit Memory Bank Control Registers Memory Bank Control Register x MBxCR = 0x014 +Optional A16, A19 Inversions by Segment /CS1 Enable MMU Instruction/Data Register Mmidr =MMU Instruction/Data Register MmidrMemory Timing Control Register MTCR, adr = MMU Expanded Code RegisterMecr Memory Timing Control RegisterAllocation of Extended Code and Data Breakpoint/Debug Control Register BDCR, adr = 0x01CBreakpoint/Debug Control Register BdcrInstruction and Data Space Support RAM Use of Physical Memory Separate I & D Space Model How the Compiler Compiles to Memory 128 Rabbit 3000 Microprocessor Parallel Ports Parallel Port a Registers Parallel Port aParallel Port a Data Register Bit Functions Parallel Port B Registers Parallel Port BParallel Port B Register Bit Functions Parallel Port C Registers Parallel Port CParallel Port C Register Bit Functions Parallel Port D Parallel Port D RegistersPD7 Parallel Port D Control Register adr = Parallel Port D Register functionsBits 7 Bits 5 Bits 3 Bits 1 136 Rabbit 3000 Microprocessor Parallel Port E PE010. Parallel Port E Registers 11. Parallel Port E Register functions 12. Parallel Port E Control Register adr =13. Parallel Port F Registers Parallel Port F14. Parallel Port F Register Functions Using Parallel Port a and Parallel Port F 15. Parallel Port F Control Register adr = 0x03CSummary Parallel Port a Parallel Port F 16. Parallel Port G Registers Parallel Port G17. Parallel Port G Data Register Functions Parallel Port G Control Register adr= 0x04C 10. I/O Bank Control Registers Write data Write strobe T1 Tw T2Read data Read strobe Chip select strobe External I/O Timing with 1 wait stateI/O Bank x Control Register External I/O Register Address Range and Pin Mapping Control Register Port E Address Pin A1513 Range148 Rabbit 3000 Microprocessor Timers Timer a Reload Register OperationTimer a I/O Registers Timer a I/O RegistersTimer a Control and Status Register Timer a CapabilitiesTacsr User’s Manual 153 Timer a Control Register Timer a Prescale RegisterTacr TaprPractical Use of Timer a Timer B Registers Timer BRegister Name Mnemonic Reset Address Timer B Control and Status Register Timer B Control RegisterTbcsr TbcrTimer B Count MSB x Registers 10. Timer B Count LSB x Registers11. Timer B Count MSB Register 12. Timer B Count LSB RegisterUsing Timer B 160 Rabbit 3000 Microprocessor Serial Port Signal Name Function Serial Port SignalsRabbit Serial Ports Clka User’s Manual 163 Signals Shown at Microprocessor Tx Pin Serial Port Register LayoutUser’s Manual 165 Serial Port Registers Serial Port a RegistersSerial Port B Registers Serial Port C RegistersSerial Port E Registers Serial Port D RegistersSerial Port F Registers Data Register All Ports Address Register All Ports10. Long Stop Register All Ports 11. Status Register Asynchronous Mode Only All Ports Bits Value Description Clocked serial mode only 12. Status Register Clocked Serial Ports A-D only13. Status Register Hdlc Mode Ports E and F only Bits Value Description Hdlc mode onlySacr 14. Serial Port Control Register Ports a and BSbcr 15. Serial Port Control Register Ports C and D SccrAddress = 0xE4 Sdcr16. Serial Port Control Register Ports E and F SecrAddress = 0xCC Sfcr17. Extended Register Asynchronous Mode All Ports 18. Extended Register Clocked Serial Mode Ports A-D only 19. Extended Register Hdlc Mode Ports E and F only Serial Port Interrupt Transmitter IRQTransmit Serial Data Timing Receive Serial Data Timing Serial Port SynchronizationClock Polarities Supported in Clocked Serial Mode Clocked Serial PortsUser’s Manual 183 184 Rabbit 3000 Microprocessor Clocked Serial Timing With Internal Clock Clocked Serial TimingClocked Serial Timing with External Clock Valid Synchronous Communications on Ports E and F Last Byte Bit Pattern Valid Data Hits User’s Manual 189 190 Rabbit 3000 Microprocessor User’s Manual 191 Serial Port Software Suggestions Push AF IOI LD A,SCSRControlling an RS-485 Driver and Receiver Transmitting Dummy CharactersUsing a Serial Port to Generate a Periodic Interrupt Transmitting and Detecting a BreakParity, Extra Stop Bits with 7-Data-Bit Characters Parity, Extra Stop Bits with 8-Data-Bit CharactersStop bit Start bit Data bits 9th bit low Stop bitRabbit-Only Master/Slave Protocol Supporting 9th Bit Communication ProtocolsData Framing/Modbus User’s Manual 197 198 Rabbit 3000 Microprocessor Rabbit Slave Port SRD SCSSlave Port Read Cycle Symbol Parameter Minimum Maximum Following table explains the parameters used in FigureSlaveattn PB7 Typical Connection Slave Rabbit to Master Rabbit Hardware Design of Slave Port Interconnection Slave Port RegistersSlave Port Registers Register Mnemonic Internal Address External AddressSlave Port Control Register Spcr adr = Bit Bits 6,5 Bit 3,2 Bits 1,0 Write Only Read OnlySlave Applications Applications and Communications Protocols for SlavesSlave Port Status Register Spsr adr = Master-Slave Messaging Protocol 208 Rabbit 3000 Microprocessor Rabbit 3000 Clocks Rabbit 3000 Main Oscillator CircuitLow-Power Design EMI Control Power Supply Connections and Board Layout Using the Clock Spectrum SpreaderSpread Spectrum Enable/Disable Register Spread Spectrum Mode SelectGCM0R GCM1R214 Rabbit 3000 Microprocessor AC Timing Specifications Memory Access TimeAccess Enable Access MHz Memory Requirements at 3.3 V, -40C to +85C, Adr Bus 60 pFVDD Data and Clock Delays VDD ±10%, Temp, -40C-+85C maximumNormal Strong 30 pF 60 pF 90 pF No dbl/dbl CSx Memory Write Time Delays Memory Read Time DelaysTime Delay Output Capacitance 30 pF 60 pF 90 pF CLK A190 CSx WEx D70 Example Clock Doubler Max-Min Clock Low Times 222 Rabbit 3000 Microprocessor 16.2 I/O Access Time BufenI/O Read Time Delays I/O Write Time DelaysFurther Discussion of Bus and Clock Timing Clock Doubler and Memory Timing Maximum Clock Speeds Maximum Clock Speeds at 3.3 V PreliminaryConditions Commercial Ratings Industrial Ratings Period FrequencyExternal Oscillator Buffer Power and Current Consumption User’s Manual 229Rabbit 3000 System Current vs. Frequency at 3.3 11. Sleepy Mode Current Consumption Current Consumption Mechanisms Sleepy Mode Current Consumption Memory Current Consumption Battery-Backed Clock Current Consumption Current is negligible for V 1.14Reduced-Power External Main Oscillator Voltage Current incl built-in bufferBios Rabbit Bios and Virtual DriverBios Services Bios Assumptions Watchdog Timer SupportVirtual Driver Periodic InterruptUser’s Manual 239 240 Rabbit 3000 Microprocessor Power Management Support Other Rabbit SoftwareUsing Library Functions Using Assembly LanguageReading and Writing I/O Registers Shadow Registers Updating Shadow RegistersInterrupt While Updating Registers Atomic InstructionWrite-only Registers Without Shadow Registers Timer and Clock UsageNon-atomic Instructions Format of the structure used is the following 246 Rabbit 3000 Microprocessor Rabbit Instructions SummarySpreadsheet Conventions Flag DescriptionSymbols Rabbit Z180 MeaningLoad Immediate Data Load & Store to Immediate Address19.3 8-bit Indexed Load and Store 19.4 16-bit Indexed Loads and Stores19.5 16-bit Load and Store 20-bit Address Register to Register MovesStack Manipulation Instructions Exchange Instructions19.9 16-bit Arithmetic and Logical Ops 19.10 8-bit Arithmetic and Logical Ops ADD A,HL19.11 8-bit Bit Set, Reset and Test 19.12 8-bit Increment and Decrement19.13 8-bit Fast a Register Operations 19.14 8-bit Shifts and RotatesInstruction Prefixes Block Move InstructionsControl Instructions Jumps and Calls Miscellaneous InstructionsPrivileged Instructions Following instructions are privilegedDifferences Rabbit VS. Z80/Z180 Instructions Z80/Z180 Instructions Dropped Rabbit Instructions to Use IOI and IOE I Column Symbol Key Flag Register KeyRabbit Z180 Meaning Z V C EX AF,AF LD A,BC LDP HL,IX RRA 268 Rabbit 3000 Microprocessor Appendix A. the Rabbit Programming Port Programming Port PIN AssignmentsUse of the Programming Port as a Diagnostic/Setup Port Alternate Programming PortSuggested Rabbit Crystal Frequencies Non-Stock Crystals Appendix B. Rabbit 3000 Revisions 274 Rabbit 3000 Microprocessor User’s Manual 275 Discussion of Fixes and Improvements Table B-1. Summary of Rabbit 3000 Improvements and FixesRabbit Description 3000 3000A IL1T/IZ1T IL2T/IZ2TTable B-2. Reset State of New Rabbit 3000A I/O Registers Rabbit Internal I/O RegistersIuer Rabbit Register Name Mnemonic 3000 3000A Address Reset Peripheral and ISR Address On-Chip Peripheral Address Range ISR Starting AddressUser’s Manual 281 Revision-Level ID Register Table B-5. Rabbit 3000 Revision Identification InformationProcessor Revision Package Gcpu GrevSystem/User Mode Memory Protection Table B-6. Write Protect Control RegisterWrite Protect Control Register WpcrWrite Protect Low Register Table B-7. Write Protect Low RegisterWplr Table B-8. Write Protect High Register Table B-9. Write Protect Segment x RegisterWphr WpsarTable B-10. Write Protect Segment x Low Register Write Protect Segment x Low RegisterWpsalr WpsblrTable B-11. Write Protect Segment x High Register Write Protect Segment x High RegisterWpsahr WpsbhrStack Protection Figure B-2. Simple Stack Protection LayoutTable B-13. Stack Low Limit Register Table B-12. Stack Limit Control RegisterTable B-14. Stack High Limit Register RAM Segment Relocation Table B-15. RAM Segment RegisterRAM Segment Register RamsrSecondary Watchdog Timer Table B-16. Watchdog Timer Control Register-UpdatedTable B-17. Secondary Watchdog Timer Register WdtcrNew Opcodes Table B-18. New Rabbit 3000 OpcodesInstruction Bytes Clks Operation New UMA/UMS OpcodesTable B-19. Rabbit 3000 Revision Block Copy Opcode Effects New Block Copy OpcodesSource Destination IOI/IOEExpanded I/O Memory Addressing Table B-20. MMU Instruction/Data RegisterExternal I/O Improvements Table B-21 Bank x Control RegisterShort Chip Select Timing for Writes Table B-22. Global Power Save Control RegisterAddress = 0x000D Table B-23. Global Control/Status Register Clock Select and Power Save ModesTable B-24. Clock Select Field of Gcsr Short Chip Select Timing Figure B-3. Short Chip Select Timing CLK/8, Read OperationFigure B-4. Short Chip Select Timing CLK/6, Read Operation Figure B-6. Short Chip Select Timing CLK/2, Read Operation Figure B-7. Short Chip Select Timing 2 kHz, Read Operation Figure B-9. Short Chip Select Timing 8 kHz, Read Operation Figure B-11. Short Chip Select Timing 32 kHz, Read Operation Figure B-12. Short Chip Select Timing CLK/8, Write Operation Figure B-13. Short Chip Select Timing CLK/6, Write Operation Figure B-15. Short Chip Select Timing CLK/2, Write Operation Figure B-16. Short Chip Select Timing 2 kHz, Write Operation Figure B-18. Short Chip Select Timing 8 kHz, Write Operation 310 Rabbit 3000 Microprocessor Pulse Width Modulator Improvements Figure B-21. PWM Interrupt and Output TimingTable B-25. PWM LSB 0 Register Table B-26. PWM LSB 1 RegisterPWM LSB 0 Register PWM LSB 1 RegisterAddress = 0x008C Table B-27. PWM LSB 2 and 3 RegistersAddress = 0x008E Quadrature Decoder Improvements Table B-28. Quadrature Decoder Control RegisterTable B-29. Quadrature Decoder Count High Register QDC1HRUser’s Manual 315 Pins with Alternate Functions Serial Ports E/FSystem Mode User Mode Appendix C. SYSTEM/USER ModeTable C-1. Differences Between System and User Modes Table C-2. New System/User Mode Opcodes System/User Mode OpcodesInstruction Bytes Clk Operation Priv System/User Mode Registers Table C-3. System/User Mode I/O RegistersTable C-4. I/O Addresses Inaccessible in User Mode Register Name Mnemonic AddressFigure C-1. Interrupt Handing in System/User Mode InterruptsPeripheral Interrupt Prioritization Table C-5. Interrupts-Priority and Action to Clear Requests Using the System/User Mode Memory Protection OnlyMixed System/User Mode Operation Figure C-3. System/User Mode Setup for Mixed OperationFigure C-4. System/User Mode Setup for Operating System Complete Operating SystemAppendix D. Rabbit 3000A Internal I/O Registers Table D-1 Rabbit 3000A Internal I/O RegistersTable D-1. Rabbit 3000A Internal I/O Registers 0x03C0 00000000 Serial Port E User Enable Register 0x006A Xxxxxxxx Port D Bit 3 Register 0x0082 00000000 Bank 3 Control Register 0x0098 Xx000000 Interrupt 1 Control Register 0x00D1 Xxxxxxxx Serial Port B Long Stop Register 334 Rabbit 3000 Microprocessor User’s Manual 335 Page Index NumericsMemory A16, A19 inversions /CS1 PWL2R, PWL3R 200