Jameco Electronics 3000, 2000 manual User’s Manual

In the case of write cycles, the chip select signals are active only around the trailing edge of the write signal. Wait states are inserted between T1 and T2, and this will have no effect on the duration of the chip select signals in this mode. The timing diagrams below illus- trate the actual timing for the different divided cases. In these cases the chip selects are active for two clock cycles before and two clock cycles after the trailing edge of the write signal.

	T1	TWA	T2
oscillator
clock
ADDR	Valid
DATA
/CSx
/WEx

divide-by-8 mode

Figure B-12. Short Chip Select Timing: CLK/8, Write Operation

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