Jameco Electronics 3000, 2000 IPSET 1, IPSET 2, IPSET, Processor, Priority, Effect on Interrupts

the same priority, this introduces interrupt latency while the next routine is waiting for the previous routine to allow more interrupts to take place. If a number of devices have inter- rupt service routines, and all interrupts are of the same priority, then pending interrupts can not take place until at least the interrupt service routine in progress is finished, or at least until it changes the interrupt priority. As a rule of thumb, Z-World usually suggests that 100 µs be allowed for interrupt latency on Z180- or Rabbit-based controllers. This can result if, for example, there are five active interrupt routines, and each turns off the inter- rupts for at most 20 µs.

The intention in the Rabbit is that most interrupting devices will use priority 1 level inter- rupts. Devices that need extremely fast response to interrupts will use priority level 2 or 3 interrupts. Since code that runs at priority level 0 or 1 never disables level 2 and level 3 interrupts, these interrupts will take place within about 20 clocks, the length of the longest instruction or longest sensible sequence of privileged instructions followed by an unprivi- leged instruction. It is important that the user be careful not to overdisable interrupts in critical code sections. The processor priority should not be raised above level 1 except in carefully considered situations.

The effect of the processor priority on interrupts is shown in Table 3-1.The priority of the interrupt is usually established by bits in an I/O control register associated with the hard- ware that creates the interrupt. The 8-bit interrupt register (IP) holds the processor priority in the least significant 2 bits. When an interrupt takes place, the IP register is shifted left 2 positions and the lower 2 bits are set to equal the priority of the interrupt that just took place. This means that an interrupt service request (ISR) can only be interrupted by an interrupt of higher priority (unless the priority is explicitly set lower by the programmer). The IP register serves as a 4-word stack of 2-bit words to save and restore interrupt priori- ties. It can be shifted right, restoring the previous priority by a special instruction (IPRES). Since only the current processor priority and 3 previous priorities can be saved in the inter- rupt register, instructions are also provided to PUSH and POP IP using the regular stack. A new priority can be “pushed” into the IP register with special instructions (IPSET 0,

IPSET 1, IPSET 2, IPSET 3).

Table 3-1. Effect of Processor Priorities on Interrupts

Processor

Priority

Effect on Interrupts

0All interrupts, priority 1,2 and 3 take place after execution of current non privileged instruction.

1Only interrupts of priority 2 and 3 take place.

2Only interrupts of priority 3 take place.

3All interrupt are suppressed (except RST instruction).

User’s Manual 45