Jameco Electronics 3000, 2000 Parallel I/O, Cascaded Output Registers for Parallel Ports D and E

2.2.5 Parallel I/O

There are 56 parallel input/output lines divided among seven 8-bit ports designated A through G. Most of the port lines have alternate functions, such as serial data or chip select strobes. Parallel Ports D, E, F, and G have the capability of timer-synchronized outputs. The output registers are cascaded as shown in Figure 2-1.

Load Data

Load Clock

Timer Clock

Output Port

Figure 2-1. Cascaded Output Registers for Parallel Ports D and E

Stores to the port are loaded in the first-level register. That register in turn is transferred to the output register on a selected timer clock. The clock can be selected to be the output of Timer A1, B1, B2 or the peripheral clock (divided by 2?). The timer signal can also cause an interrupt that can be used to set up the next bit to be output on the next timer pulse. This feature can be used to generate precisely controlled pulses whose edges are positioned with high accuracy in time. Applications include communications signaling, pulse width modulation and driving stepper motors. (A separate pulse width modulation facility is also included in the Rabbit 3000.)

External Input

D Q

D Q

Filtered Input

peripheral clock

Figure 2-2. Digital Filtering Input Pins

Input pins to the parallel ports are filtered by cascaded D flip flops as shown in Figure 2-2.This prevents pulses shorter then the peripheral clock from being recognized, synchro- nizes external pulses to the internal clock, and avoids problems with meta stability (tem- porarily indeterminate logical conditions due to marginal set up time with respect to the clock).

User’s Manual 13