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Jameco Electronics 3000, 2000 manual Rabbit Slave Port, SD0-SD7

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13.RABBIT SLAVE PORT

13.RABBIT SLAVE PORT

When a Rabbit microprocessor is configured as a slave, Parallel Port A and certain other data lines are used as communication lines between the slave and the master. The slave unit is a Rabbit configured as a slave. The master can be another Rabbit or any other type of processor. Rabbits configured as slaves can themselves have slaves.

The master and slave communicate with each other via the slave port. The slave port is a physical device that includes data registers, a data bus and various handshaking lines. The slave port is a part of the slave Rabbit, but logically it is an independent device that is used to communicate between the two processors. A diagram of the slave port is shown in Figure 13-1.

			SPSR
	81-88		SPD2R
		SD0-SD7
	98
		SA1	SPD1R
	97
		SA0
	95
		/SWR	SPD0R
	96
		/SRD
	21
		/SCS	CPU

	100	/SLAVEATTN

Figure 13-1. Rabbit Slave Port

The slave port has three data registers for each direction of communication. Three regis- ters, named SPD0R, SPD1R, and SPD2R, can be written by the master and read by the slave. Three different registers, also named SPD0R, SPD1R, and SPD2R, can be written by the slave and read by the master. The same names are used for different registers since it is usually clear from the context which register is meant. If it is necessary to distinguish between registers, we will refer to the registers as “SPD0R writable by the slave” or “SPD0R writable by the master.”

User’s Manual

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Jameco Electronics 3000, 2000 manual Rabbit Slave Port, SD0-SD7

Contents

Distributed by Rabbit 3000 Microprocessor User’s ManualRabbit Semiconductor TrademarksRabbit 3000 Microprocessor User’s Manual Chapter 2. Rabbit 3000 Design Features TABLE OF CONTENTSChapter 1. Introduction Chapter 4. Rabbit Capabilities Parallel Ports Chapter 14. Rabbit 3000 Clocks Appendix A. The Rabbit Programming Port Rabbit 3000 Microprocessor 1. INTRODUCTION User’s Manual1.1 Features and Specifications Rabbit Rabbit 3000 MicroprocessorUser’s Manual •There is a built-inwatchdog timer Figure 1-1.Rabbit 3000 Block Diagram User’s Manual1.2 Summary of Rabbit 3000 Advantages 1.3 Differences Rabbit 3000 vs. Rabbit FeatureRabbit RabbitFeature RabbitRabbit Serial ports with support for SDLC/HDLC IrDA2.RABBIT 3000 DESIGN FEATURES User’s ManualRabbit 3000 Microprocessor 2.2.1 5 V Tolerant Inputs 2.2 Overview of On-ChipPeripherals and Features2.2.2 Serial Ports 2.2.4 32.768 kHz Oscillator Input 2.2.3 System ClockRabbit 3000 Microprocessor 2.2.5 Parallel I/O Figure 2-2.Digital Filtering Input PinsExternal Input Filtered Input2.2.6 Slave Port Rabbit2.2.8 Timers 2.2.7 Auxiliary I/O Bus2.2.9 Input Capture Channels Figure 2-4.Rabbit Timers A and B2.2.11 Pulse Width Modulation Outputs 2.2.10 Quadrature Encoder InputsUser’s Manual 2.2.13 Separate Core and I/O Power Pins 2.3 Design Standards2.2.12 Spread Spectrum Clock 2.3.1 Programming Port2.3.2 Standard BIOS 2.4 Dynamic C Support for the RabbitRabbit 3000 Microprocessor 3.DETAILS ON RABBIT MICROPROCESSOR FEATURES 3.1Processor RegistersRabbit 3000 Microprocessor 3.2 Memory Mapping Figure 3-3.Example of Memory Mapping Operation Figure 3-4 shows a memory interface unit 3.2.1 Extended Code Space Rabbit 3000 MicroprocessorCompiler notices that Compiler insertscode has passed F000 long jump in codexpc window stack 3.2.3 Using the Stack Segment for Data Storage Data RAM Root Code 3.2.4 Practical Memory ConsiderationsData RAM Root Code User’s Manual 3.3 Instruction Set Outline 3.3.1 Load Immediate Data to a Register User’s Manual3.3.3 Load or Store Data Using an Index Register 3.3.5 Register Exchanges 3.3.4 Register-to-RegisterMoveUser’s Manual 3.3.6 Push and Pop Instructions 3.3.7 16-bitArithmetic and Logical OpsUser’s Manual extend sign of l to HL 3.3.8 Input/Output Instructions User’s Manual3.4.2Exchanges Not Directly Implemented 3.4.1 Zero HL in 4 Clocks3.4.3 Manipulation of Boolean Variables 3.4.4 Comparisons of Integers User’s Manualtest for 3.4.5 Atomic Moves from Memory to I/O Space 3.5 Interrupt Structure 3.5.1 Interrupt PriorityIPSET 1, IPSET 2, IPSET ProcessorPriority Effect on InterruptsLD SP,HL LD SP,IY LD SP,IX 3.5.2 Multiple External Interrupting DevicesLD SP,HL IOI LD sseg,a 3.5.5 Semaphores Using Bit B,HL 3.5.4 Critical Sections3.5.6 Computed Long Calls and Jumps 4.RABBIT CAPABILITIES 4.1 Precisely Timed Output PulsesRabbit 2000 Microprocessor 4.2 Open-DrainOutputs Used for Key Scan 4.3 Cold Boot Rabbit 2000 Microprocessor4.4 The Slave Port User’s Manual4.4.1 Slave Rabbit As A Protocol UART Rabbit 2000 Microprocessor5.PIN ASSIGNMENTS AND FUNCTIONS User’s Manual5.1.1 Pinout 5.1 LQFP PackageRabbit 3000 Microprocessor 5.1.2 Mechanical Dimensions and Land Pattern 16.00 ± 0.25 mm14.00 ± 0.10 mm 14.00 ± 0.10 mmTOLERANCE AND SOLDER JOINT ANALYSIS Toe FilletHeel Fillet Side Fillet5.2 Ball Grid Array Package 5.2.1 PinoutA B C D E F G H J K L M User’s Manual5.2.2 Mechanical Dimensions and Land Pattern Table 5-2.Ball and Land Size Dimensionsall dimensions in mm Table 5-3.Design ConsiderationsFigure 5-5.BGA Package Outline User’s ManualTOP VIEW BOTTOM VIEW5.3 Rabbit Pin Descriptions Table 5-1.Rabbit Pin DescriptionsTable 5-1.Rabbit Pin Descriptions continued 5.4 Bus Timing Figure 5-6.Bus Timing Read and Write5.5 Description of Pins with Alternate Functions Table 5-2.Pins With Alternate FunctionsTable 5-2.Pins With Alternate Functions continued Table 5-3.Parallel Port x Alternate Functions Table 5-6.3.3 Volt DC Characteristics 5.6 DC CharacteristicsTable 5-5.Rabbit 3000 Absolute Maximum Ratings 5.7 I/O Buffer Sourcing and Sinking Limit User’s ManualRabbit 3000 Microprocessor 6.RABBIT INTERNAL I/O REGISTERS User’s ManualOn-ChipPeripheral ISR Starting AddressReset Table 6-2.Rabbit Internal I/O RegistersRegister Name MnemonicTable 6-2.Rabbit Internal I/O Registers continued Table 6-2.Rabbit Internal I/O Registers continued Port E Bit 7 RegisterTable 6-2.Rabbit Internal I/O Registers continued PWM MSB 0 RegisterTimer A Time Constant 5 Register Table 6-2.Rabbit Internal I/O Registers continuedTable 6-2.Rabbit Internal I/O Registers continued Serial Port D Address Register7.MISCELLANEOUS FUNCTIONS 7.1Processor Identification7.2 Rabbit Oscillators and Clocks Main ClockRabbit 32.768 kHz ClockTable 7-5.Global Control/Status Register Table 7-6.Clock Select Field of GCSR7.3 Clock Doubler Table 7-7.Global Clock Double RegisterOscillator Oscillator delayed and inverted User’s Manual 7.4 Clock Spectrum Spreader 7.5 Chip Select Options for Low Power User’s ManualGlobal Power Save Control Register GPSCRAddress = 0x0D BitsFigure 7-4.Short Chip Select Memory Read 32 kHzADDR Valid7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN 7.7 Time/Date Clock Real-TimeClock User’s ManualTable 7-10. Real-TimeClock RTCxR Data Registers 7.8 Watchdog Timer 0x51 7.9 System Reset User’s ManualRESET Low Post-Reset†Pin Name Direction7.10 Rabbit Interrupt Structure Interrupt Source PriorityAction Required to Clear the Interrupt 7.10.1 External Interrupts Reg Name Reg AddressBits 7,6 Bits 5,47.11 Bootstrap Operation User’s ManualRabbit 3000 Microprocessor 7.12 Pulse Width Modulator Table 7-17.PWM LSB x Register Table 7-18.PWM MSB x Register7.13 Input Capture Timer A8CPT input InterruptRabbit 3000 Microprocessor Table 7-19.Input Capture Control/Status Register Input Capture Control/Status RegisterICCSR Address =Table 7-20.Input Capture Control Register Table 7-21.Input Capture Trigger x RegisterTable 7-23.Input Capture LSB x Register Table 7-22.Input Capture Source x RegisterTable 7-24.Input Capture MSB x Register 7.14 Quadrature Decoder I inputQ input Counter 00Accepted RejectedUser’s Manual Quad Decode Control/Status Register QDCSRAddress = BitsTable 7-26.Quadrature Decoder Control Register Table 7-27.Quadrature Decoder Count RegisterRabbit 3000 Microprocessor 8.MEMORY INTERFACE AND MAPPING 8.1Interface for Static Memory ChipsRabbit Figure 8-2.Typical Memory Chip Connection8.2 Memory Mapping Overview 8.3 Memory-MappingUnitProcessor Memory Mapping UnitPage 8.4 Memory Interface Unit User’s Manual8.5 Memory Bank Control Registers Table 8-4.MMU Instruction/Data Register MMIDR = MMU Instruction/Data RegisterMMIDR Address =Table 8-5.MMU Expanded Code Register MECR = 8.6 Allocation of Extended Code and Data Breakpoint/Debug Control RegisterBDCR Address = 0x01C8.7 Instruction and Data Space Support Bits 7:5Combined I & D 64k+4*n 8.8 How the Compiler Compiles to Memory User’s ManualRabbit 3000 Microprocessor 9. PARALLEL PORTS 9.1 Parallel Port A 9.2 Parallel Port B Table 9-5.Parallel Port C Registers 9.3 Parallel Port CTable 9-6.Parallel Port C Register Bit Functions 9.4 Parallel Port D Table 9-7.Parallel Port D Registersperclk/2 Timer A1 Timer B1 Timer B2 PD3 PD0 perclk/2 Timer A1 Timer B1 Timer B2Figure 9-1.Parallel Port D Block Diagram I/O DataTable 9-8.Parallel Port D Register functions Table 9-9.Parallel Port D Control Register adr =•PDDR—ParallelPort D data register. Read/Write 9.5 Parallel Port E Table 9-10.Parallel Port E Registers Rabbit 3000 MicroprocessorTable 9-11.Parallel Port E Register functions Table 9-12.Parallel Port E Control Register adr =Table 9-13.Parallel Port F Registers 9.6 Parallel Port FTable 9-14.Parallel Port F Register Functions 9.6.1 Using Parallel Port A and Parallel Port F User’s Manual• Parallel Inputs • Full Functionality• Parallel Outputs • Parallel Inputs, PWM, Serial Port Clocks9.7 Parallel Port G Table 9-16.Parallel Port G RegistersParallel Port G Control Register adr= 0x04C TableRabbit 3000 Microprocessor 10.I/O BANK CONTROL REGISTERS ADDR write data write strobeT1 Tw T2 read data read strobe chip select strobeTable 10-1.I/O Bank x Control Register Control Register Port EI/O Address I/O AddressRabbit 3000 Microprocessor 11. TIMERS Figure 11-1.Block Diagram of Timers A and B11.1 Timer A 11.1.1 Timer A I/O Registers Table 11-3.Timer A Control and Status Register Timer A CapabilitiesTable A4 interrupt disabled Table 11-4.Timer A Control Register Table 11-5.Timer A Prescale Register11.1.2 Practical Use of Timer A User’s Manual11.2 Timer B Table 11-7.Timer B Control and Status Register Table 11-8.Timer B Control RegisterTable 11-9.Timer B Count MSB x Registers Table 11-10.Timer B Count LSB x RegistersTable 11-11.Timer B Count MSB Register Table 11-12.Timer B Count LSB Register11.2.1 Using Timer B Rabbit 3000 Microprocessor 12.RABBIT SERIAL PORTS Table 12-1.Serial Port SignalsCLKA Timer A4 Serial Port A TXA User’s Manual 12.1 Serial Port Register Layout User’s Manual 12.2 Serial Port Registers Table 12-2.Serial Port A RegistersTable 12-3.Serial Port B Registers Table 12-4.Serial Port C RegistersTable 12-6.Serial Port E Registers Table 12-5.Serial Port D RegistersTable 12-7.Serial Port F Registers Table 12-8.Data Register All Ports Table 12-9.Address Register All PortsTable 12-10.Long Stop Register All Ports Serial Port x Status Register Serial Port x Status Register Description HDLC mode only Serial Port x Status RegisterSESR Address = 0xCBSerial Port x Control Register SACRAddress = 0xC4 SBCRSerial Port x Control Register SCCRAddress = 0xE4 SDCRSerial Port x Control Register SECRAddress = 0xCC SFCRSerial Port x Extended Register Normal clocked serial operation Normal HDLC data encoding Transmitter IRQ 12.3 Serial Port InterruptRequest Interrupt 12.4 Transmit Serial Data Timing Rabbit 3000 Microprocessor12.5 Receive Serial Data Timing 12.6 Clocked Serial Ports User’s Manual Rabbit 3000 Microprocessor 12.7.1 Clocked Serial Timing With Internal Clock 12.7 Clocked Serial Timing12.7.2 Clocked Serial Timing with External Clock perclk CLKAValid Rabbit 3000 Microprocessor12.8 Synchronous Communications on Ports E and F User’s ManualLast Byte Bit Pattern Valid Data HitsUser’s Manual Rabbit 3000 Microprocessor User’s Manual 12.9 Serial Port Software Suggestions 12.9.2 Transmitting Dummy Characters 12.9.1 Controlling an RS-485Driver and ReceiverUser’s Manual 12.9.3 Transmitting and Detecting a Break stop bit 7 12.9.8 Supporting 9th Bit Communication Protocols 12.9.9 Rabbit-OnlyMaster/Slave Protocol12.9.10 Data Framing/Modbus Rabbit 3000 MicroprocessorUser’s Manual Rabbit 3000 Microprocessor 13.RABBIT SLAVE PORT SD0-SD7Slave Port Read Cycle Slave Port Write CycleSA1, SA0 SRD SD7:0Symbol ParameterMinimum MaximumMaster writes SPD0R Reset Master RabbitFirst Slave Rabbit D0–D713.2 Slave Port Registers Table 13-1.Slave Port RegistersThe functionality of the bits is as follows 13.3.1 Slave Applications Table 13-3.Slave Port Status Register SPSR adr =13.3.2 Master-SlaveMessaging Protocol User’s ManualRabbit 3000 Microprocessor 14.RABBIT 3000 CLOCKS Figure 14-1.Rabbit 3000 Main Oscillator Circuit14.1 Low-PowerDesign Rabbit 3000 Microprocessor15. EMI CONTROL User’s Manual15.1 Power Supply Connections and Board Layout 15.2 Using the Clock Spectrum SpreaderTable 15-2.Spread Spectrum Mode Select Rabbit 3000 Microprocessor 16.AC TIMING SPECIFICATIONS 16.1 Memory Access Timedelay CSx WEx D7:0 CLK A19:0D7:0 Tsetup•T = -40Cto 85C, V = 3.3 D7:0 CLK A19:0 CSx WEx D7:0Tsetup CLK A19:0Example Min. delay @ 3.3 V = 3.7 + 0.75n - Max. delay @ 2.5 V = 7.6 + 1.67n -Min. delay @ 2.5 V = 4.7 + 1.03n - Max. delay @ 1.8 V = 12.2 + 2.7n -Example •Clock = 29.49 MHz •T = 34 ns16.2 I/O Access Time CLK A15:0IOCSx IORDThe following I/O read time delays were measured 16.3 Further Discussion of Bus and Clock Timing User’s ManualOscillator Oscillator delayed and inverted 16.4 Maximum Clock Speeds +3.3 XTALA1 Figure 16-8.External Oscillator Buffer16.5 Power and Current Consumption User’s Manualenlarged view over 0–16MHz range 32MHz and 1.4 µA at 2 kHz 16.6 Current Consumption Mechanisms Rabbit 3000 Microprocessor16.7 Sleepy Mode Current Consumption Itotal µA = 0.32 × V × f + 0.23 × Vc × f + 5 × Vc16.8 Memory Current Consumption 16.9 Battery-BackedClock Current Consumption 16.10 Reduced-PowerExternal Main Oscillator Design Recommendations17.1 The BIOS 17.RABBIT BIOS AND VIRTUAL DRIVER17.1.1 BIOS Services 17.1.2 BIOS Assumptions 17.2.2 Watchdog Timer Support17.2 Virtual Driver 17.2.1 Periodic InterruptUser’s Manual Rabbit 3000 Microprocessor 18.1Power Management Support 18.OTHER RABBIT SOFTWARE18.2.2 Using Library Functions 18.2.1 Using Assembly Language18.2 Reading and Writing I/O Registers 18.3.1 Updating Shadow Registers 18.3 Shadow Registers18.3.2 Interrupt While Updating Registers 18.4 Timer and Clock Usage 18.3.2.2 Non-atomicInstructionsThe format of the structure used is the following Rabbit 3000 Microprocessor 19.RABBIT INSTRUCTIONS SummarySpreadsheet Conventions ALTD “A” Column Symbol KeyIOI and IOE “I” Column Symbol Key Flag Register KeySymbols RabbitZ180 Meaning19.1 Load Immediate Data 19.2 Load & Store to Immediate Address19.3 8-bitIndexed Load and Store 19.4 16-bitIndexed Loads and Stores19.6 Register to Register Moves 19.5 16-bitLoad and Store 20-bitAddressUser’s Manual 19.8 Stack Manipulation Instructions 19.7 Exchange Instructions19.9 16-bitArithmetic and Logical Ops 19.10 8-bitArithmetic and Logical Ops User’s Manual19.118-bitBit Set, Reset and Test 19.12 8-bitIncrement and Decrement19.14 8-bitShifts and Rotates 19.13 8-bitFast A Register OperationsUser’s Manual 19.15 Instruction Prefixes 19.16 Block Move Instructions19.18 Miscellaneous Instructions 19.17 Control Instructions - Jumps and CallsUser’s Manual 19.19 Privileged Instructions 20.DIFFERENCES RABBIT VS. Z80/Z180 INSTRUCTIONS Z80/Z180 Instructions Dropped Rabbit Instructions to UseALTD “A” Column Symbol Key IOI and IOE “I” Column Symbol KeySpreadsheet Conventions Flag Register KeySymbols Bit selectInstruction Instruction Instruction Instruction Instruction Rabbit 3000 Microprocessor Rabbit LQFP pins are shown in parenthesis APPENDIX A. THE RABBIT PROGRAMMING PORTPROGRAMMING PORT PIN ASSIGNMENTS A.2 Alternate Programming Port Rabbit 3000 Microprocessor•spectrum spreader set to normal A.3 Suggested Rabbit Crystal Frequencies•doubler in use 52/48 duty cycle, and Memory Access Times, and Baud Rates Table A-1.Preliminary Crystal FrequenciesAPPENDIX B. RABBIT 3000 REVISIONS User’s ManualRabbit 3000 Microprocessor User’s Manual B.1 Discussion of Fixes and Improvements RabbitRabbit DescriptionB.1.1 Rabbit Internal I/O Registers ResetRegister Name MnemonicExternal Interrupt User Enable Register Global Power Save Control Register and Interrupt Service Vectors B.1.2 Peripheral and ISR AddressTable B-4.Rabbit 3000 I/O Address Ranges and Interrupt Service Vectors continued continued Table B-4.Rabbit 3000 I/O Address RangesB.1.3 Revision-LevelID Register Processor RevisionPackage GCPUB.1.4 System/User Mode User’s ManualB.1.5 Memory Protection Table B-7.Write Protect Low Register Write Protect Low RegisterWPLR Address =Table B-8.Write Protect High Register Table B-9.Write Protect Segment x RegisterTable B-10.Write Protect Segment x Low Register Write Protect Segment x Low RegisterWPSALR Address =Table B-11.Write Protect Segment x High Register Write Protect Segment x High RegisterWPSAHR Address =B.1.6 Stack Protection Table B-13.Stack Low Limit Register Table B-12.Stack Limit Control RegisterTable B-14.Stack High Limit Register B.1.7 RAM Segment Relocation Table B-15.RAM Segment RegisterB.1.8 Secondary Watchdog Timer Table B-17.Secondary Watchdog Timer RegisterB.1.9 New Opcodes LDDSRLDISR LSDRLDDR LDIRLSDR LSIRB.1.10 Expanded I/O Memory Addressing Table B-20.MMU Instruction/Data RegisterTable B-21 B.1.11 External I/O ImprovementsI/O Bank x Control Register B.1.12 Short Chip Select Timing for Writes Table B-22.Global Power Save Control RegisterTable B-23.Global Control/Status Register Table B-24.Clock Select Field of GCSRB.1.12.2 Short Chip Select Timing User’s Manualo s c illa to r oscillator 32 kHz 32 kHz 32 kHz clockADDR ValidUser’s Manual oscillator oscillator 32KkHz User’s Manual 32 kHz B.1.13 Pulse Width Modulator Improvements Figure B-21.PWM Interrupt and Output TimingTable B-25.PWM LSB 0 Register Table B-26.PWM LSB 1 RegisterTable B-27.PWM LSB 2 and 3 Registers PWM LSB x RegisterPWL2R Address = 0x008CTable B-28.Quadrature Decoder Control Register B.1.14 Quadrature Decoder ImprovementsTable B-29.Quadrature Decoder Count High Register User’s Manual I inputQ input Cnt 8 bitB.2 Pins with Alternate Functions System Mode APPENDIX C. SYSTEM/USER MODEUser Mode C.1 System/User Mode Opcodes C.2 System/User Mode Registers Table C-3.System/User Mode I/O RegistersTable C-4.I/O Addresses Inaccessible in User Mode INTERRUPT UNDER SYSTEM CONTROL C.3 InterruptsINTERRUPT UNDER USER CONTROL C.3.1 Peripheral Interrupt Prioritization Rabbit 3000 MicroprocessorInterrupt Source PriorityAction required to clear the interrupt C.4 Using the System/User Mode C.4.1 Memory Protection OnlyC.4.2 Mixed System/User Mode Operation User’s ManualInterrupt C.4.3 Complete Operating SystemSYSCALL Table D-1 APPENDIX D. RABBIT 3000A INTERNAL I/O REGISTERSRabbit 3000A Internal I/O Registers Rabbit 3000 Microprocessor I/O Bank User Enable Register Port D Bit 2 Register I/O Bank 2 Control Register Interrupt 0 Control Register Serial Port B Address Register Rabbit 3000 Microprocessor NOTICE TO USERS User’s ManualPage INDEX NumericsPage TATxR