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Jameco Electronics 3000, 2000 manual C.3 Interrupts, Interrupt Under System Control

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C.3 Interrupts

C.3 Interrupts

When enabled for User mode access, a peripheral interrupt (if it is capable of generating an interrupt) can only be requested at Interrupt Priority Level -2 or -1. Interrupts (and RSTs and SYSCALL) all enter the System mode automatically. There will be times, however, that an interrupt should be handled in the User mode. The solution to this is for the System mode interrupt vector to reenter User mode before calling the User mode interrupt handler. An example of both system and user interrupt handling is shown in Figure C-1.

INTERRUPT UNDER SYSTEM CONTROL
ISR (system)
Application code (user)	Application code (user)
INTERRUPT UNDER USER CONTROL
ISR (system)
Application ISR (user)
Application code (user)	Application code (user)

Figure C-1. Interrupt Handing in System/User Mode

Some sample code for both System mode interrupts and User mode interrupts is shown below.

system_isr:	; jumped to from interrupt vector table
... handle interrupt ...
sures	; reenter previous mode
ret
user_isr:	; jumped to from interrupt vector table
push su	; preserve current SU stack
setusr	; enter user mode
... handle interrupt ...
pop su	; restore previous SU stack
sures	; reenter previous mode
ret

User’s Manual

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Jameco Electronics 3000, 2000 manual C.3 Interrupts, Interrupt Under System Control, Interrupt Under User Control

Contents

Distributed by Rabbit 3000 Microprocessor User’s ManualTrademarks Rabbit SemiconductorRabbit 3000 Microprocessor User’s Manual TABLE OF CONTENTS Chapter 2. Rabbit 3000 Design FeaturesChapter 1. Introduction Chapter 4. Rabbit Capabilities Parallel Ports Chapter 14. Rabbit 3000 Clocks Appendix A. The Rabbit Programming Port Rabbit 3000 Microprocessor 1. INTRODUCTION User’s Manual1.1 Features and Specifications Rabbit Rabbit 3000 MicroprocessorUser’s Manual •There is a built-inwatchdog timer Figure 1-1.Rabbit 3000 Block Diagram User’s Manual1.2 Summary of Rabbit 3000 Advantages Rabbit 1.3 Differences Rabbit 3000 vs. RabbitFeature RabbitRabbit FeatureRabbit Serial ports with support for SDLC/HDLC IrDA2.RABBIT 3000 DESIGN FEATURES User’s ManualRabbit 3000 Microprocessor 2.2 Overview of On-ChipPeripherals and Features 2.2.1 5 V Tolerant Inputs2.2.2 Serial Ports 2.2.3 System Clock 2.2.4 32.768 kHz Oscillator InputRabbit 3000 Microprocessor External Input 2.2.5 Parallel I/OFigure 2-2.Digital Filtering Input Pins Filtered Input2.2.6 Slave Port Rabbit2.2.8 Timers 2.2.7 Auxiliary I/O Bus2.2.9 Input Capture Channels Figure 2-4.Rabbit Timers A and B2.2.10 Quadrature Encoder Inputs 2.2.11 Pulse Width Modulation OutputsUser’s Manual 2.2.12 Spread Spectrum Clock 2.2.13 Separate Core and I/O Power Pins2.3 Design Standards 2.3.1 Programming Port2.3.2 Standard BIOS 2.4 Dynamic C Support for the RabbitRabbit 3000 Microprocessor 3.DETAILS ON RABBIT MICROPROCESSOR FEATURES 3.1Processor RegistersRabbit 3000 Microprocessor 3.2 Memory Mapping Figure 3-3.Example of Memory Mapping Operation Figure 3-4 shows a memory interface unit 3.2.1 Extended Code Space Rabbit 3000 Microprocessorcode has passed F000 Compiler notices thatCompiler inserts long jump in codexpc window stack 3.2.3 Using the Stack Segment for Data Storage 3.2.4 Practical Memory Considerations Data RAM Root CodeData RAM Root Code User’s Manual 3.3 Instruction Set Outline 3.3.1 Load Immediate Data to a Register User’s Manual3.3.3 Load or Store Data Using an Index Register 3.3.4 Register-to-RegisterMove 3.3.5 Register ExchangesUser’s Manual 3.3.6 Push and Pop Instructions 3.3.7 16-bitArithmetic and Logical OpsUser’s Manual extend sign of l to HL 3.3.8 Input/Output Instructions User’s Manual3.4.1 Zero HL in 4 Clocks 3.4.2Exchanges Not Directly Implemented3.4.3 Manipulation of Boolean Variables 3.4.4 Comparisons of Integers User’s Manualtest for 3.4.5 Atomic Moves from Memory to I/O Space 3.5 Interrupt Structure 3.5.1 Interrupt PriorityPriority IPSET 1, IPSET 2, IPSETProcessor Effect on Interrupts3.5.2 Multiple External Interrupting Devices LD SP,HL LD SP,IY LD SP,IXLD SP,HL IOI LD sseg,a 3.5.5 Semaphores Using Bit B,HL 3.5.4 Critical Sections3.5.6 Computed Long Calls and Jumps 4.RABBIT CAPABILITIES 4.1 Precisely Timed Output PulsesRabbit 2000 Microprocessor 4.2 Open-DrainOutputs Used for Key Scan 4.3 Cold Boot Rabbit 2000 Microprocessor4.4 The Slave Port User’s Manual4.4.1 Slave Rabbit As A Protocol UART Rabbit 2000 Microprocessor5.PIN ASSIGNMENTS AND FUNCTIONS User’s Manual5.1 LQFP Package 5.1.1 PinoutRabbit 3000 Microprocessor 14.00 ± 0.10 mm 5.1.2 Mechanical Dimensions and Land Pattern16.00 ± 0.25 mm 14.00 ± 0.10 mmHeel Fillet TOLERANCE AND SOLDER JOINT ANALYSISToe Fillet Side FilletA B C D E F G H J K L M 5.2 Ball Grid Array Package5.2.1 Pinout User’s Manualall dimensions in mm 5.2.2 Mechanical Dimensions and Land PatternTable 5-2.Ball and Land Size Dimensions Table 5-3.Design ConsiderationsTOP VIEW Figure 5-5.BGA Package OutlineUser’s Manual BOTTOM VIEW5.3 Rabbit Pin Descriptions Table 5-1.Rabbit Pin DescriptionsTable 5-1.Rabbit Pin Descriptions continued 5.4 Bus Timing Figure 5-6.Bus Timing Read and Write5.5 Description of Pins with Alternate Functions Table 5-2.Pins With Alternate FunctionsTable 5-2.Pins With Alternate Functions continued Table 5-3.Parallel Port x Alternate Functions 5.6 DC Characteristics Table 5-6.3.3 Volt DC CharacteristicsTable 5-5.Rabbit 3000 Absolute Maximum Ratings 5.7 I/O Buffer Sourcing and Sinking Limit User’s ManualRabbit 3000 Microprocessor 6.RABBIT INTERNAL I/O REGISTERS User’s ManualOn-ChipPeripheral ISR Starting AddressRegister Name ResetTable 6-2.Rabbit Internal I/O Registers MnemonicTable 6-2.Rabbit Internal I/O Registers continued Table 6-2.Rabbit Internal I/O Registers continued Port E Bit 7 RegisterTable 6-2.Rabbit Internal I/O Registers continued PWM MSB 0 RegisterTimer A Time Constant 5 Register Table 6-2.Rabbit Internal I/O Registers continuedTable 6-2.Rabbit Internal I/O Registers continued Serial Port D Address Register7.MISCELLANEOUS FUNCTIONS 7.1Processor Identification7.2 Rabbit Oscillators and Clocks Main ClockRabbit 32.768 kHz ClockTable 7-5.Global Control/Status Register Table 7-6.Clock Select Field of GCSR7.3 Clock Doubler Table 7-7.Global Clock Double RegisterOscillator Oscillator delayed and inverted User’s Manual 7.4 Clock Spectrum Spreader 7.5 Chip Select Options for Low Power User’s ManualAddress = 0x0D Global Power Save Control RegisterGPSCR BitsADDR Figure 7-4.Short Chip Select Memory Read32 kHz Valid7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN 7.7 Time/Date Clock Real-TimeClock User’s ManualTable 7-10. Real-TimeClock RTCxR Data Registers 7.8 Watchdog Timer 0x51 7.9 System Reset User’s ManualPin Name RESET LowPost-Reset† Direction7.10 Rabbit Interrupt Structure Priority Interrupt SourceAction Required to Clear the Interrupt 7.10.1 External Interrupts Bits 7,6 Reg NameReg Address Bits 5,47.11 Bootstrap Operation User’s ManualRabbit 3000 Microprocessor 7.12 Pulse Width Modulator Table 7-17.PWM LSB x Register Table 7-18.PWM MSB x RegisterCPT input 7.13 Input CaptureTimer A8 InterruptRabbit 3000 Microprocessor ICCSR Table 7-19.Input Capture Control/Status RegisterInput Capture Control/Status Register Address =Table 7-20.Input Capture Control Register Table 7-21.Input Capture Trigger x RegisterTable 7-22.Input Capture Source x Register Table 7-23.Input Capture LSB x RegisterTable 7-24.Input Capture MSB x Register Q input 7.14 Quadrature DecoderI input Counter 00Rejected AcceptedUser’s Manual Address = Quad Decode Control/Status RegisterQDCSR BitsTable 7-26.Quadrature Decoder Control Register Table 7-27.Quadrature Decoder Count RegisterRabbit 3000 Microprocessor 8.MEMORY INTERFACE AND MAPPING 8.1Interface for Static Memory ChipsRabbit Figure 8-2.Typical Memory Chip ConnectionProcessor 8.2 Memory Mapping Overview8.3 Memory-MappingUnit Memory Mapping UnitPage 8.4 Memory Interface Unit User’s Manual8.5 Memory Bank Control Registers MMIDR Table 8-4.MMU Instruction/Data Register MMIDR =MMU Instruction/Data Register Address =Table 8-5.MMU Expanded Code Register MECR = BDCR 8.6 Allocation of Extended Code and DataBreakpoint/Debug Control Register Address = 0x01C8.7 Instruction and Data Space Support Bits 7:5Combined I & D 64k+4*n 8.8 How the Compiler Compiles to Memory User’s ManualRabbit 3000 Microprocessor 9. PARALLEL PORTS 9.1 Parallel Port A 9.2 Parallel Port B 9.3 Parallel Port C Table 9-5.Parallel Port C RegistersTable 9-6.Parallel Port C Register Bit Functions 9.4 Parallel Port D Table 9-7.Parallel Port D RegistersFigure 9-1.Parallel Port D Block Diagram perclk/2 Timer A1 Timer B1 Timer B2PD3 PD0 perclk/2 Timer A1 Timer B1 Timer B2 I/O DataTable 9-8.Parallel Port D Register functions Table 9-9.Parallel Port D Control Register adr =•PDDR—ParallelPort D data register. Read/Write 9.5 Parallel Port E Table 9-10.Parallel Port E Registers Rabbit 3000 MicroprocessorTable 9-11.Parallel Port E Register functions Table 9-12.Parallel Port E Control Register adr =9.6 Parallel Port F Table 9-13.Parallel Port F RegistersTable 9-14.Parallel Port F Register Functions 9.6.1 Using Parallel Port A and Parallel Port F User’s Manual• Parallel Outputs • Parallel Inputs• Full Functionality • Parallel Inputs, PWM, Serial Port Clocks9.7 Parallel Port G Table 9-16.Parallel Port G RegistersTable Parallel Port G Control Register adr= 0x04CRabbit 3000 Microprocessor T1 Tw T2 10.I/O BANK CONTROL REGISTERSADDR write data write strobe read data read strobe chip select strobeTable 10-1.I/O Bank x Control Register I/O Address Control RegisterPort E I/O AddressRabbit 3000 Microprocessor 11. TIMERS Figure 11-1.Block Diagram of Timers A and B11.1 Timer A 11.1.1 Timer A I/O Registers Timer A Capabilities Table 11-3.Timer A Control and Status RegisterTable A4 interrupt disabled Table 11-4.Timer A Control Register Table 11-5.Timer A Prescale Register11.1.2 Practical Use of Timer A User’s Manual11.2 Timer B Table 11-7.Timer B Control and Status Register Table 11-8.Timer B Control RegisterTable 11-11.Timer B Count MSB Register Table 11-9.Timer B Count MSB x RegistersTable 11-10.Timer B Count LSB x Registers Table 11-12.Timer B Count LSB Register11.2.1 Using Timer B Rabbit 3000 Microprocessor 12.RABBIT SERIAL PORTS Table 12-1.Serial Port SignalsCLKA Timer A4 Serial Port A TXA User’s Manual 12.1 Serial Port Register Layout User’s Manual Table 12-3.Serial Port B Registers 12.2 Serial Port RegistersTable 12-2.Serial Port A Registers Table 12-4.Serial Port C RegistersTable 12-5.Serial Port D Registers Table 12-6.Serial Port E RegistersTable 12-7.Serial Port F Registers Table 12-8.Data Register All Ports Table 12-9.Address Register All PortsTable 12-10.Long Stop Register All Ports Serial Port x Status Register Serial Port x Status Register SESR Description HDLC mode onlySerial Port x Status Register Address = 0xCBAddress = 0xC4 Serial Port x Control RegisterSACR SBCRAddress = 0xE4 Serial Port x Control RegisterSCCR SDCRAddress = 0xCC Serial Port x Control RegisterSECR SFCRSerial Port x Extended Register Normal clocked serial operation Normal HDLC data encoding 12.3 Serial Port Interrupt Transmitter IRQRequest Interrupt 12.4 Transmit Serial Data Timing Rabbit 3000 Microprocessor12.5 Receive Serial Data Timing 12.6 Clocked Serial Ports User’s Manual Rabbit 3000 Microprocessor 12.7 Clocked Serial Timing 12.7.1 Clocked Serial Timing With Internal Clock12.7.2 Clocked Serial Timing with External Clock Valid perclkCLKA Rabbit 3000 Microprocessor12.8 Synchronous Communications on Ports E and F User’s ManualLast Byte Bit Pattern Valid Data HitsUser’s Manual Rabbit 3000 Microprocessor User’s Manual 12.9 Serial Port Software Suggestions 12.9.1 Controlling an RS-485Driver and Receiver 12.9.2 Transmitting Dummy CharactersUser’s Manual 12.9.3 Transmitting and Detecting a Break stop bit 7 12.9.10 Data Framing/Modbus 12.9.8 Supporting 9th Bit Communication Protocols12.9.9 Rabbit-OnlyMaster/Slave Protocol Rabbit 3000 MicroprocessorUser’s Manual Rabbit 3000 Microprocessor 13.RABBIT SLAVE PORT SD0-SD7SA1, SA0 Slave Port Read CycleSlave Port Write Cycle SRD SD7:0Minimum SymbolParameter MaximumMaster writes SPD0R First Slave Rabbit ResetMaster Rabbit D0–D713.2 Slave Port Registers Table 13-1.Slave Port RegistersThe functionality of the bits is as follows 13.3.1 Slave Applications Table 13-3.Slave Port Status Register SPSR adr =13.3.2 Master-SlaveMessaging Protocol User’s ManualRabbit 3000 Microprocessor 14.RABBIT 3000 CLOCKS Figure 14-1.Rabbit 3000 Main Oscillator Circuit14.1 Low-PowerDesign Rabbit 3000 Microprocessor15. EMI CONTROL User’s Manual15.1 Power Supply Connections and Board Layout 15.2 Using the Clock Spectrum SpreaderTable 15-2.Spread Spectrum Mode Select Rabbit 3000 Microprocessor 16.AC TIMING SPECIFICATIONS 16.1 Memory Access Timedelay D7:0 CSx WEx D7:0CLK A19:0 Tsetup•T = -40Cto 85C, V = 3.3 Tsetup D7:0CLK A19:0 CSx WEx D7:0 CLK A19:0Example Min. delay @ 2.5 V = 4.7 + 1.03n - Min. delay @ 3.3 V = 3.7 + 0.75n -Max. delay @ 2.5 V = 7.6 + 1.67n - Max. delay @ 1.8 V = 12.2 + 2.7n -Example •Clock = 29.49 MHz •T = 34 nsIOCSx 16.2 I/O Access TimeCLK A15:0 IORDThe following I/O read time delays were measured 16.3 Further Discussion of Bus and Clock Timing User’s ManualOscillator Oscillator delayed and inverted 16.4 Maximum Clock Speeds +3.3 XTALA1 Figure 16-8.External Oscillator Buffer16.5 Power and Current Consumption User’s Manualenlarged view over 0–16MHz range 32MHz and 1.4 µA at 2 kHz 16.6 Current Consumption Mechanisms Rabbit 3000 Microprocessor16.7 Sleepy Mode Current Consumption Itotal µA = 0.32 × V × f + 0.23 × Vc × f + 5 × Vc16.8 Memory Current Consumption 16.9 Battery-BackedClock Current Consumption 16.10 Reduced-PowerExternal Main Oscillator Design Recommendations17.RABBIT BIOS AND VIRTUAL DRIVER 17.1 The BIOS17.1.1 BIOS Services 17.2 Virtual Driver 17.1.2 BIOS Assumptions17.2.2 Watchdog Timer Support 17.2.1 Periodic InterruptUser’s Manual Rabbit 3000 Microprocessor 18.1Power Management Support 18.OTHER RABBIT SOFTWARE18.2.1 Using Assembly Language 18.2.2 Using Library Functions18.2 Reading and Writing I/O Registers 18.3 Shadow Registers 18.3.1 Updating Shadow Registers18.3.2 Interrupt While Updating Registers 18.4 Timer and Clock Usage 18.3.2.2 Non-atomicInstructionsThe format of the structure used is the following Rabbit 3000 Microprocessor 19.RABBIT INSTRUCTIONS SummaryIOI and IOE “I” Column Symbol Key Spreadsheet ConventionsALTD “A” Column Symbol Key Flag Register KeyZ180 SymbolsRabbit Meaning19.3 8-bitIndexed Load and Store 19.1 Load Immediate Data19.2 Load & Store to Immediate Address 19.4 16-bitIndexed Loads and Stores19.5 16-bitLoad and Store 20-bitAddress 19.6 Register to Register MovesUser’s Manual 19.7 Exchange Instructions 19.8 Stack Manipulation Instructions19.9 16-bitArithmetic and Logical Ops 19.10 8-bitArithmetic and Logical Ops User’s Manual19.118-bitBit Set, Reset and Test 19.12 8-bitIncrement and Decrement19.13 8-bitFast A Register Operations 19.14 8-bitShifts and RotatesUser’s Manual 19.15 Instruction Prefixes 19.16 Block Move Instructions19.17 Control Instructions - Jumps and Calls 19.18 Miscellaneous InstructionsUser’s Manual 19.19 Privileged Instructions 20.DIFFERENCES RABBIT VS. Z80/Z180 INSTRUCTIONS Z80/Z180 Instructions Dropped Rabbit Instructions to UseSpreadsheet Conventions ALTD “A” Column Symbol KeyIOI and IOE “I” Column Symbol Key Flag Register KeySymbols Bit selectInstruction Instruction Instruction Instruction Instruction Rabbit 3000 Microprocessor APPENDIX A. THE RABBIT PROGRAMMING PORT Rabbit LQFP pins are shown in parenthesisPROGRAMMING PORT PIN ASSIGNMENTS A.2 Alternate Programming Port Rabbit 3000 MicroprocessorA.3 Suggested Rabbit Crystal Frequencies •spectrum spreader set to normal•doubler in use 52/48 duty cycle, and Memory Access Times, and Baud Rates Table A-1.Preliminary Crystal FrequenciesAPPENDIX B. RABBIT 3000 REVISIONS User’s ManualRabbit 3000 Microprocessor User’s Manual Rabbit B.1 Discussion of Fixes and ImprovementsRabbit DescriptionRegister Name B.1.1 Rabbit Internal I/O RegistersReset MnemonicExternal Interrupt User Enable Register Global Power Save Control Register B.1.2 Peripheral and ISR Address and Interrupt Service VectorsTable B-4.Rabbit 3000 I/O Address Ranges and Interrupt Service Vectors continued continued Table B-4.Rabbit 3000 I/O Address RangesPackage B.1.3 Revision-LevelID RegisterProcessor Revision GCPUB.1.4 System/User Mode User’s ManualB.1.5 Memory Protection WPLR Table B-7.Write Protect Low RegisterWrite Protect Low Register Address =Table B-8.Write Protect High Register Table B-9.Write Protect Segment x RegisterWPSALR Table B-10.Write Protect Segment x Low RegisterWrite Protect Segment x Low Register Address =WPSAHR Table B-11.Write Protect Segment x High RegisterWrite Protect Segment x High Register Address =B.1.6 Stack Protection Table B-12.Stack Limit Control Register Table B-13.Stack Low Limit RegisterTable B-14.Stack High Limit Register B.1.7 RAM Segment Relocation Table B-15.RAM Segment RegisterB.1.8 Secondary Watchdog Timer Table B-17.Secondary Watchdog Timer RegisterLDISR B.1.9 New OpcodesLDDSR LSDRLSDR LDDRLDIR LSIRB.1.10 Expanded I/O Memory Addressing Table B-20.MMU Instruction/Data RegisterB.1.11 External I/O Improvements Table B-21I/O Bank x Control Register B.1.12 Short Chip Select Timing for Writes Table B-22.Global Power Save Control RegisterTable B-23.Global Control/Status Register Table B-24.Clock Select Field of GCSRB.1.12.2 Short Chip Select Timing User’s Manualo s c illa to r oscillator 32 kHz 32 kHz ADDR 32 kHzclock ValidUser’s Manual oscillator oscillator 32KkHz User’s Manual 32 kHz B.1.13 Pulse Width Modulator Improvements Figure B-21.PWM Interrupt and Output TimingTable B-25.PWM LSB 0 Register Table B-26.PWM LSB 1 RegisterPWL2R Table B-27.PWM LSB 2 and 3 RegistersPWM LSB x Register Address = 0x008CB.1.14 Quadrature Decoder Improvements Table B-28.Quadrature Decoder Control RegisterTable B-29.Quadrature Decoder Count High Register Q input User’s ManualI input Cnt 8 bitB.2 Pins with Alternate Functions APPENDIX C. SYSTEM/USER MODE System ModeUser Mode C.1 System/User Mode Opcodes C.2 System/User Mode Registers Table C-3.System/User Mode I/O RegistersTable C-4.I/O Addresses Inaccessible in User Mode C.3 Interrupts INTERRUPT UNDER SYSTEM CONTROLINTERRUPT UNDER USER CONTROL C.3.1 Peripheral Interrupt Prioritization Rabbit 3000 MicroprocessorPriority Interrupt SourceAction required to clear the interrupt C.4 Using the System/User Mode C.4.1 Memory Protection OnlyC.4.2 Mixed System/User Mode Operation User’s ManualC.4.3 Complete Operating System InterruptSYSCALL APPENDIX D. RABBIT 3000A INTERNAL I/O REGISTERS Table D-1Rabbit 3000A Internal I/O Registers Rabbit 3000 Microprocessor I/O Bank User Enable Register Port D Bit 2 Register I/O Bank 2 Control Register Interrupt 0 Control Register Serial Port B Address Register Rabbit 3000 Microprocessor NOTICE TO USERS User’s ManualPage INDEX NumericsPage TATxR