Jameco Electronics 2000, 3000 manual Memory Bank Control Registers

8.5 Memory Bank Control Registers

Table 8-3describes the operation of the four memory bank control registers. The registers are write-only. Each register controls one quadrant in the 1M address space.

Table 8-3. Memory Bank Control Register x (MBxCR = 0x014 + x)

Memory Bank x Control Register			(MB0CR)	(Address = 0x014)
			(MB1CR)	(Address = 0x015)
			(MB2CR)	(Address = 0x016)
			(MB3CR)	(Address = 0x017)
Bit(s)	Value		Description
	00	Four wait states for accesses in this bank.
7:6	01	Two wait states for accesses in this bank.
	10	One wait states for accesses in this bank.
	11	Zero wait states for accesses in this bank.
5	0	Pass A[19] for accesses in this bank.
	1	Invert A[19] for accesses in this bank.
4	0	Pass A[18] for accesses in this bank.
	1	Invert A[18] for accesses in this bank.
	00	/OE0 and /WE0 are active for accesses in this bank
	01	/OE1 and /WE1 are active for accesses in this bank
3:2	10	/OE0 only is active for accesses in this bank (i.e. read-only). Transactions are
		normal in every other way.
	11	/OE1 only is active for accesses in this bank (i.e. read-only). Transactions are
		normal in every other way.
	00	/CS0 is active for accesses in this bank.
1:0	01	/CS1 is active for accesses in this bank.
	1x	/CS2 is active for accesses in this bank.

Bits 7,6—The number of wait states used in access to this quadrant. Without wait states, read requires 2 clocks and write requires 3 clocks. The wait state adds to these numbers. Wait states should only be used for memory data accesses (RAM or data flash), not for memory from which instructions are executed (code memory).

Bits 5, 4—These bits allow the upper address lines to be inverted. This inversion occurs after the logic that selects the bank register, so setting these lines has no effect on which bank register is used. The inversion may be used to install a 1M memory chip in the space normally allocated to a 256K chip. The larger memory can then be accessed as 4 pages of 256K each. There is no effect outside the quadrant that the memory bank control register is controlling.

120 Rabbit 3000 Microprocessor