Figure 16-2and Figure 16-3illustrate the memory read and write cycles. The Rabbit 3000 operates at 2 clocks per bus cycle plus any wait states that might be specified.

Memory Read (no wait states)

T1

T2

CLK A[19:0]

valid

Tadr

/CSx

 

TCSx

TCSx

/OEx

 

TOEx

TOEx

D[7:0]

Tsetup

valid

 

Thold

Memory Write (no extra wait states)

T1

Tw

T2

CLK A[19:0]

/CSx

/WEx

D[7:0]

valid

 

 

 

 

 

 

Tadr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCSx

TCSx

 

 

 

 

 

 

 

 

 

 

 

 

TWEx

TWEx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

valid

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDHZV

TDVHZ

 

 

 

 

 

 

 

 

 

 

 

Figure 16-2. Memory Read and Write Cycles

User’s Manual

217

Page 226
Image 226
Jameco Electronics 3000, 2000 manual CSx