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Jameco Electronics 2000, 3000 manual C.1 System/User Mode Opcodes

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C.1 System/User Mode Opcodes

Seven new opcodes have been added to support the System/User mode, and are listed in Table C-2.All but IDET are placed in previously empty opcode table assignments. IDET shares the value of LD E,E in the opcode table, and will perform that operation when the System/User mode is disabled, or when it is enabled and in the System mode. In addition, if the ALTD prefix appears before the opcode, LD E’,E is always executed instead.

The processor keeps a one-byte stack (called the SU register) that is analogous to the IP register that keeps track of the interrupt priority. Every time SETUSR is executed (to enter the User mode), or an interrupt occurs, or SYSCALL or RST is executed (to enter the Sys- tem mode), the current mode is pushed onto the SU register. When a SURES is executed, the previous mode is popped off the SU register.

The effects of each opcode are:

•The SETUSR opcode puts the processor into the User mode by pushing the correct value into the SU register.

•PUSH SU and POP SU push and pop the single-byte SU register on/off the SP stack.

•SURES pops the current processor mode off the SU register, returning it to the previous mode.

•IDET causes an interrupt if executed in the User mode, and does nothing in the System mode.

•RDMODE returns the current mode in the carry flag (0 for System mode, 1 for User mode).

•SYSCALL is essentially a new RST opcode, and was added to allow User mode access to the System mode without using one of the existing RST opcodes. It will put the processor into the System mode and execute code in the corresponding interrupt-vector table entry.

Table C-2. New System/User Mode Opcodes

	Instruction	Bytes	clk	A	I	S	Z	V	C	Operation	Priv
	Instruction	Bytes	clk	A	I	S	Z	V	C	Operation	?
											?

	SETUSR	2	4		-	-	-	-	-	SU = {SU[5:0], 0x01}	Yes

	PUSH SU	2	9		-	-	-	-	-	(SP-1) = SU; SP = SP - 1	Yes

	POP SU	2	7		-	-	-	-	-	SU = (SP); SP = SP + 1	Yes

	SURES	2	4		-	-	-	-	-	SU = {SU[1:0], SU[7:2]}	Yes

										Performs LD E,E, but if
	IDET	1	2		-	-	-	-	-	(EDMF && SU[0]) then the System	No
										Violation interrupt flag is set; if ALTD
										appears before it always does LD E’,E

	RDMODE	2	4		-	-	-	-	*	CF = SU[0]	Yes

	SYSCALL	2	10		-	-	-	-	-	SP = SP - 2; PC = {R,v} where	No
	SYSCALL	2	10		-	-	-	-	-	v = SYSCALL offset	No

318	Rabbit 3000 Microprocessor

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Jameco Electronics 2000, 3000 manual C.1 System/User Mode Opcodes

Contents

Distributed by User’s Manual Rabbit 3000 MicroprocessorTrademarks Rabbit SemiconductorRabbit 3000 Microprocessor User’s Manual TABLE OF CONTENTS Chapter 2. Rabbit 3000 Design FeaturesChapter 1. Introduction Chapter 4. Rabbit Capabilities Parallel Ports Chapter 14. Rabbit 3000 Clocks Appendix A. The Rabbit Programming Port Rabbit 3000 Microprocessor User’s Manual 1. INTRODUCTIONRabbit 3000 Microprocessor 1.1 Features and Specifications RabbitUser’s Manual There is a built-inwatchdog timer User’s Manual Figure 1-1.Rabbit 3000 Block Diagram1.2 Summary of Rabbit 3000 Advantages Rabbit 1.3 Differences Rabbit 3000 vs. RabbitFeature RabbitSerial ports with support for SDLC/HDLC IrDA FeatureRabbit RabbitUser’s Manual 2.RABBIT 3000 DESIGN FEATURESRabbit 3000 Microprocessor 2.2 Overview of On-ChipPeripherals and Features 2.2.1 5 V Tolerant Inputs2.2.2 Serial Ports 2.2.3 System Clock 2.2.4 32.768 kHz Oscillator InputRabbit 3000 Microprocessor Filtered Input 2.2.5 Parallel I/OFigure 2-2.Digital Filtering Input Pins External InputRabbit 2.2.6 Slave Port2.2.7 Auxiliary I/O Bus 2.2.8 TimersFigure 2-4.Rabbit Timers A and B 2.2.9 Input Capture Channels2.2.10 Quadrature Encoder Inputs 2.2.11 Pulse Width Modulation OutputsUser’s Manual 2.3.1 Programming Port 2.2.13 Separate Core and I/O Power Pins2.3 Design Standards 2.2.12 Spread Spectrum Clock2.4 Dynamic C Support for the Rabbit 2.3.2 Standard BIOSRabbit 3000 Microprocessor 3.1Processor Registers 3.DETAILS ON RABBIT MICROPROCESSOR FEATURESRabbit 3000 Microprocessor 3.2 Memory Mapping Figure 3-3.Example of Memory Mapping Operation Figure 3-4 shows a memory interface unit Rabbit 3000 Microprocessor 3.2.1 Extended Code Spacelong jump in code Compiler notices thatCompiler inserts code has passed F000xpc window stack 3.2.3 Using the Stack Segment for Data Storage 3.2.4 Practical Memory Considerations Data RAM Root CodeData RAM Root Code User’s Manual 3.3 Instruction Set Outline User’s Manual 3.3.1 Load Immediate Data to a Register3.3.3 Load or Store Data Using an Index Register 3.3.4 Register-to-RegisterMove 3.3.5 Register ExchangesUser’s Manual 3.3.7 16-bitArithmetic and Logical Ops 3.3.6 Push and Pop InstructionsUser’s Manual extend sign of l to HL User’s Manual 3.3.8 Input/Output Instructions3.4.1 Zero HL in 4 Clocks 3.4.2Exchanges Not Directly Implemented3.4.3 Manipulation of Boolean Variables User’s Manual 3.4.4 Comparisons of Integerstest for 3.4.5 Atomic Moves from Memory to I/O Space 3.5.1 Interrupt Priority 3.5 Interrupt StructureEffect on Interrupts IPSET 1, IPSET 2, IPSETProcessor Priority3.5.2 Multiple External Interrupting Devices LD SP,HL LD SP,IY LD SP,IXLD SP,HL IOI LD sseg,a 3.5.4 Critical Sections 3.5.5 Semaphores Using Bit B,HL3.5.6 Computed Long Calls and Jumps 4.1 Precisely Timed Output Pulses 4.RABBIT CAPABILITIESRabbit 2000 Microprocessor 4.2 Open-DrainOutputs Used for Key Scan Rabbit 2000 Microprocessor 4.3 Cold BootUser’s Manual 4.4 The Slave PortRabbit 2000 Microprocessor 4.4.1 Slave Rabbit As A Protocol UARTUser’s Manual 5.PIN ASSIGNMENTS AND FUNCTIONS5.1 LQFP Package 5.1.1 PinoutRabbit 3000 Microprocessor 14.00 ± 0.10 mm 5.1.2 Mechanical Dimensions and Land Pattern16.00 ± 0.25 mm 14.00 ± 0.10 mmSide Fillet TOLERANCE AND SOLDER JOINT ANALYSISToe Fillet Heel FilletUser’s Manual 5.2 Ball Grid Array Package5.2.1 Pinout A B C D E F G H J K L MTable 5-3.Design Considerations 5.2.2 Mechanical Dimensions and Land PatternTable 5-2.Ball and Land Size Dimensions all dimensions in mmBOTTOM VIEW Figure 5-5.BGA Package OutlineUser’s Manual TOP VIEWTable 5-1.Rabbit Pin Descriptions 5.3 Rabbit Pin DescriptionsTable 5-1.Rabbit Pin Descriptions continued Figure 5-6.Bus Timing Read and Write 5.4 Bus TimingTable 5-2.Pins With Alternate Functions 5.5 Description of Pins with Alternate FunctionsTable 5-2.Pins With Alternate Functions continued Table 5-3.Parallel Port x Alternate Functions 5.6 DC Characteristics Table 5-6.3.3 Volt DC CharacteristicsTable 5-5.Rabbit 3000 Absolute Maximum Ratings User’s Manual 5.7 I/O Buffer Sourcing and Sinking LimitRabbit 3000 Microprocessor User’s Manual 6.RABBIT INTERNAL I/O REGISTERSISR Starting Address On-ChipPeripheralMnemonic ResetTable 6-2.Rabbit Internal I/O Registers Register NameTable 6-2.Rabbit Internal I/O Registers continued Port E Bit 7 Register Table 6-2.Rabbit Internal I/O Registers continuedPWM MSB 0 Register Table 6-2.Rabbit Internal I/O Registers continuedTable 6-2.Rabbit Internal I/O Registers continued Timer A Time Constant 5 RegisterSerial Port D Address Register Table 6-2.Rabbit Internal I/O Registers continued7.1Processor Identification 7.MISCELLANEOUS FUNCTIONSMain Clock 7.2 Rabbit Oscillators and Clocks32.768 kHz Clock RabbitTable 7-6.Clock Select Field of GCSR Table 7-5.Global Control/Status RegisterTable 7-7.Global Clock Double Register 7.3 Clock DoublerOscillator Oscillator delayed and inverted User’s Manual 7.4 Clock Spectrum Spreader User’s Manual 7.5 Chip Select Options for Low PowerBits Global Power Save Control RegisterGPSCR Address = 0x0DValid Figure 7-4.Short Chip Select Memory Read32 kHz ADDR7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN User’s Manual 7.7 Time/Date Clock Real-TimeClockTable 7-10. Real-TimeClock RTCxR Data Registers 7.8 Watchdog Timer 0x51 User’s Manual 7.9 System ResetDirection RESET LowPost-Reset† Pin Name7.10 Rabbit Interrupt Structure Priority Interrupt SourceAction Required to Clear the Interrupt 7.10.1 External Interrupts Bits 5,4 Reg NameReg Address Bits 7,6User’s Manual 7.11 Bootstrap OperationRabbit 3000 Microprocessor 7.12 Pulse Width Modulator Table 7-18.PWM MSB x Register Table 7-17.PWM LSB x RegisterInterrupt 7.13 Input CaptureTimer A8 CPT inputRabbit 3000 Microprocessor Address = Table 7-19.Input Capture Control/Status RegisterInput Capture Control/Status Register ICCSRTable 7-21.Input Capture Trigger x Register Table 7-20.Input Capture Control RegisterTable 7-22.Input Capture Source x Register Table 7-23.Input Capture LSB x RegisterTable 7-24.Input Capture MSB x Register Counter 00 7.14 Quadrature DecoderI input Q inputRejected AcceptedUser’s Manual Bits Quad Decode Control/Status RegisterQDCSR Address =Table 7-27.Quadrature Decoder Count Register Table 7-26.Quadrature Decoder Control RegisterRabbit 3000 Microprocessor 8.1Interface for Static Memory Chips 8.MEMORY INTERFACE AND MAPPINGFigure 8-2.Typical Memory Chip Connection RabbitMemory Mapping Unit 8.2 Memory Mapping Overview8.3 Memory-MappingUnit ProcessorPage User’s Manual 8.4 Memory Interface Unit8.5 Memory Bank Control Registers Address = Table 8-4.MMU Instruction/Data Register MMIDR =MMU Instruction/Data Register MMIDRTable 8-5.MMU Expanded Code Register MECR = Address = 0x01C 8.6 Allocation of Extended Code and DataBreakpoint/Debug Control Register BDCRBits 7:5 8.7 Instruction and Data Space SupportCombined I & D 64k+4*n User’s Manual 8.8 How the Compiler Compiles to MemoryRabbit 3000 Microprocessor 9. PARALLEL PORTS 9.1 Parallel Port A 9.2 Parallel Port B 9.3 Parallel Port C Table 9-5.Parallel Port C RegistersTable 9-6.Parallel Port C Register Bit Functions Table 9-7.Parallel Port D Registers 9.4 Parallel Port DI/O Data perclk/2 Timer A1 Timer B1 Timer B2PD3 PD0 perclk/2 Timer A1 Timer B1 Timer B2 Figure 9-1.Parallel Port D Block DiagramTable 9-9.Parallel Port D Control Register adr = Table 9-8.Parallel Port D Register functions•PDDR—ParallelPort D data register. Read/Write 9.5 Parallel Port E Rabbit 3000 Microprocessor Table 9-10.Parallel Port E RegistersTable 9-12.Parallel Port E Control Register adr = Table 9-11.Parallel Port E Register functions9.6 Parallel Port F Table 9-13.Parallel Port F RegistersTable 9-14.Parallel Port F Register Functions User’s Manual 9.6.1 Using Parallel Port A and Parallel Port F• Parallel Inputs, PWM, Serial Port Clocks • Parallel Inputs• Full Functionality • Parallel OutputsTable 9-16.Parallel Port G Registers 9.7 Parallel Port GTable Parallel Port G Control Register adr= 0x04CRabbit 3000 Microprocessor read data read strobe chip select strobe 10.I/O BANK CONTROL REGISTERSADDR write data write strobe T1 Tw T2Table 10-1.I/O Bank x Control Register I/O Address Control RegisterPort E I/O AddressRabbit 3000 Microprocessor Figure 11-1.Block Diagram of Timers A and B 11. TIMERS11.1 Timer A 11.1.1 Timer A I/O Registers Timer A Capabilities Table 11-3.Timer A Control and Status RegisterTable A4 interrupt disabled Table 11-5.Timer A Prescale Register Table 11-4.Timer A Control RegisterUser’s Manual 11.1.2 Practical Use of Timer A11.2 Timer B Table 11-8.Timer B Control Register Table 11-7.Timer B Control and Status RegisterTable 11-12.Timer B Count LSB Register Table 11-9.Timer B Count MSB x RegistersTable 11-10.Timer B Count LSB x Registers Table 11-11.Timer B Count MSB Register11.2.1 Using Timer B Rabbit 3000 Microprocessor Table 12-1.Serial Port Signals 12.RABBIT SERIAL PORTSCLKA Timer A4 Serial Port A TXA User’s Manual 12.1 Serial Port Register Layout User’s Manual Table 12-4.Serial Port C Registers 12.2 Serial Port RegistersTable 12-2.Serial Port A Registers Table 12-3.Serial Port B RegistersTable 12-5.Serial Port D Registers Table 12-6.Serial Port E RegistersTable 12-7.Serial Port F Registers Table 12-9.Address Register All Ports Table 12-8.Data Register All PortsTable 12-10.Long Stop Register All Ports Serial Port x Status Register Serial Port x Status Register SFSR Serial Port x Status RegisterSESR Address = 0xCBSBCR Serial Port x Control RegisterSACR Address = 0xC4SDCR Serial Port x Control RegisterSCCR Address = 0xE4SFCR Serial Port x Control RegisterSECR Address = 0xCCSerial Port x Extended Register Normal clocked serial operation Normal HDLC data encoding 12.3 Serial Port Interrupt Transmitter IRQRequest Interrupt Rabbit 3000 Microprocessor 12.4 Transmit Serial Data Timing12.5 Receive Serial Data Timing 12.6 Clocked Serial Ports User’s Manual Rabbit 3000 Microprocessor 12.7 Clocked Serial Timing 12.7.1 Clocked Serial Timing With Internal Clock12.7.2 Clocked Serial Timing with External Clock Rabbit 3000 Microprocessor perclkCLKA ValidUser’s Manual 12.8 Synchronous Communications on Ports E and FValid Data Hits Last Byte Bit PatternUser’s Manual Rabbit 3000 Microprocessor User’s Manual 12.9 Serial Port Software Suggestions 12.9.1 Controlling an RS-485Driver and Receiver 12.9.2 Transmitting Dummy CharactersUser’s Manual 12.9.3 Transmitting and Detecting a Break stop bit 7 Rabbit 3000 Microprocessor 12.9.8 Supporting 9th Bit Communication Protocols12.9.9 Rabbit-OnlyMaster/Slave Protocol 12.9.10 Data Framing/ModbusUser’s Manual Rabbit 3000 Microprocessor SD0-SD7 13.RABBIT SLAVE PORTSRD SD7:0 Slave Port Read CycleSlave Port Write Cycle SA1, SA0Maximum SymbolParameter MinimumMaster writes SPD0R D0–D7 ResetMaster Rabbit First Slave RabbitTable 13-1.Slave Port Registers 13.2 Slave Port RegistersThe functionality of the bits is as follows Table 13-3.Slave Port Status Register SPSR adr = 13.3.1 Slave ApplicationsUser’s Manual 13.3.2 Master-SlaveMessaging ProtocolRabbit 3000 Microprocessor Figure 14-1.Rabbit 3000 Main Oscillator Circuit 14.RABBIT 3000 CLOCKSRabbit 3000 Microprocessor 14.1 Low-PowerDesignUser’s Manual 15. EMI CONTROL15.2 Using the Clock Spectrum Spreader 15.1 Power Supply Connections and Board LayoutTable 15-2.Spread Spectrum Mode Select Rabbit 3000 Microprocessor 16.1 Memory Access Time 16.AC TIMING SPECIFICATIONSdelay Tsetup CSx WEx D7:0CLK A19:0 D7:0•T = -40Cto 85C, V = 3.3 CLK A19:0 D7:0CLK A19:0 CSx WEx D7:0 TsetupExample Max. delay @ 1.8 V = 12.2 + 2.7n - Min. delay @ 3.3 V = 3.7 + 0.75n -Max. delay @ 2.5 V = 7.6 + 1.67n - Min. delay @ 2.5 V = 4.7 + 1.03n -•Clock = 29.49 MHz •T = 34 ns ExampleIORD 16.2 I/O Access TimeCLK A15:0 IOCSxThe following I/O read time delays were measured User’s Manual 16.3 Further Discussion of Bus and Clock TimingOscillator Oscillator delayed and inverted 16.4 Maximum Clock Speeds Figure 16-8.External Oscillator Buffer +3.3 XTALA1User’s Manual 16.5 Power and Current Consumptionenlarged view over 0–16MHz range 32MHz and 1.4 µA at 2 kHz Rabbit 3000 Microprocessor 16.6 Current Consumption MechanismsItotal µA = 0.32 × V × f + 0.23 × Vc × f + 5 × Vc 16.7 Sleepy Mode Current Consumption16.8 Memory Current Consumption 16.9 Battery-BackedClock Current Consumption Design Recommendations 16.10 Reduced-PowerExternal Main Oscillator17.RABBIT BIOS AND VIRTUAL DRIVER 17.1 The BIOS17.1.1 BIOS Services 17.2.1 Periodic Interrupt 17.1.2 BIOS Assumptions17.2.2 Watchdog Timer Support 17.2 Virtual DriverUser’s Manual Rabbit 3000 Microprocessor 18.OTHER RABBIT SOFTWARE 18.1Power Management Support18.2.1 Using Assembly Language 18.2.2 Using Library Functions18.2 Reading and Writing I/O Registers 18.3 Shadow Registers 18.3.1 Updating Shadow Registers18.3.2 Interrupt While Updating Registers 18.3.2.2 Non-atomicInstructions 18.4 Timer and Clock UsageThe format of the structure used is the following Rabbit 3000 Microprocessor Summary 19.RABBIT INSTRUCTIONSFlag Register Key Spreadsheet ConventionsALTD “A” Column Symbol Key IOI and IOE “I” Column Symbol KeyMeaning SymbolsRabbit Z18019.4 16-bitIndexed Loads and Stores 19.1 Load Immediate Data19.2 Load & Store to Immediate Address 19.3 8-bitIndexed Load and Store19.5 16-bitLoad and Store 20-bitAddress 19.6 Register to Register MovesUser’s Manual 19.7 Exchange Instructions 19.8 Stack Manipulation Instructions19.9 16-bitArithmetic and Logical Ops User’s Manual 19.10 8-bitArithmetic and Logical Ops19.12 8-bitIncrement and Decrement 19.118-bitBit Set, Reset and Test19.13 8-bitFast A Register Operations 19.14 8-bitShifts and RotatesUser’s Manual 19.16 Block Move Instructions 19.15 Instruction Prefixes19.17 Control Instructions - Jumps and Calls 19.18 Miscellaneous InstructionsUser’s Manual 19.19 Privileged Instructions 20.DIFFERENCES RABBIT VS. Z80/Z180 INSTRUCTIONS Rabbit Instructions to Use Z80/Z180 Instructions DroppedFlag Register Key ALTD “A” Column Symbol KeyIOI and IOE “I” Column Symbol Key Spreadsheet ConventionsBit select SymbolsInstruction Instruction Instruction Instruction Instruction Rabbit 3000 Microprocessor APPENDIX A. THE RABBIT PROGRAMMING PORT Rabbit LQFP pins are shown in parenthesisPROGRAMMING PORT PIN ASSIGNMENTS Rabbit 3000 Microprocessor A.2 Alternate Programming PortA.3 Suggested Rabbit Crystal Frequencies •spectrum spreader set to normal•doubler in use 52/48 duty cycle, and Table A-1.Preliminary Crystal Frequencies Memory Access Times, and Baud RatesUser’s Manual APPENDIX B. RABBIT 3000 REVISIONSRabbit 3000 Microprocessor User’s Manual Description B.1 Discussion of Fixes and ImprovementsRabbit RabbitMnemonic B.1.1 Rabbit Internal I/O RegistersReset Register NameExternal Interrupt User Enable Register Global Power Save Control Register B.1.2 Peripheral and ISR Address and Interrupt Service VectorsTable B-4.Rabbit 3000 I/O Address Ranges Table B-4.Rabbit 3000 I/O Address Ranges and Interrupt Service Vectors continued continuedGCPU B.1.3 Revision-LevelID RegisterProcessor Revision PackageUser’s Manual B.1.4 System/User ModeB.1.5 Memory Protection Address = Table B-7.Write Protect Low RegisterWrite Protect Low Register WPLRTable B-9.Write Protect Segment x Register Table B-8.Write Protect High RegisterAddress = Table B-10.Write Protect Segment x Low RegisterWrite Protect Segment x Low Register WPSALRAddress = Table B-11.Write Protect Segment x High RegisterWrite Protect Segment x High Register WPSAHRB.1.6 Stack Protection Table B-12.Stack Limit Control Register Table B-13.Stack Low Limit RegisterTable B-14.Stack High Limit Register Table B-15.RAM Segment Register B.1.7 RAM Segment RelocationTable B-17.Secondary Watchdog Timer Register B.1.8 Secondary Watchdog TimerLSDR B.1.9 New OpcodesLDDSR LDISRLSIR LDDRLDIR LSDRTable B-20.MMU Instruction/Data Register B.1.10 Expanded I/O Memory AddressingB.1.11 External I/O Improvements Table B-21I/O Bank x Control Register Table B-22.Global Power Save Control Register B.1.12 Short Chip Select Timing for WritesTable B-24.Clock Select Field of GCSR Table B-23.Global Control/Status RegisterUser’s Manual B.1.12.2 Short Chip Select Timingo s c illa to r oscillator 32 kHz 32 kHz Valid 32 kHzclock ADDRUser’s Manual oscillator oscillator 32KkHz User’s Manual 32 kHz Figure B-21.PWM Interrupt and Output Timing B.1.13 Pulse Width Modulator ImprovementsTable B-26.PWM LSB 1 Register Table B-25.PWM LSB 0 RegisterAddress = 0x008C Table B-27.PWM LSB 2 and 3 RegistersPWM LSB x Register PWL2RB.1.14 Quadrature Decoder Improvements Table B-28.Quadrature Decoder Control RegisterTable B-29.Quadrature Decoder Count High Register Cnt 8 bit User’s ManualI input Q inputB.2 Pins with Alternate Functions APPENDIX C. SYSTEM/USER MODE System ModeUser Mode C.1 System/User Mode Opcodes Table C-3.System/User Mode I/O Registers C.2 System/User Mode RegistersTable C-4.I/O Addresses Inaccessible in User Mode C.3 Interrupts INTERRUPT UNDER SYSTEM CONTROLINTERRUPT UNDER USER CONTROL Rabbit 3000 Microprocessor C.3.1 Peripheral Interrupt PrioritizationPriority Interrupt SourceAction required to clear the interrupt C.4.1 Memory Protection Only C.4 Using the System/User ModeUser’s Manual C.4.2 Mixed System/User Mode OperationC.4.3 Complete Operating System InterruptSYSCALL APPENDIX D. RABBIT 3000A INTERNAL I/O REGISTERS Table D-1Rabbit 3000A Internal I/O Registers Rabbit 3000 Microprocessor I/O Bank User Enable Register Port D Bit 2 Register I/O Bank 2 Control Register Interrupt 0 Control Register Serial Port B Address Register Rabbit 3000 Microprocessor User’s Manual NOTICE TO USERSPage Numerics INDEXPage TATxR