Jameco Electronics 3000, 2000 manual Default Values for all the Peripheral Control Registers

6.1 Default Values for all the Peripheral Control Registers

The default values for all of the peripheral control registers are shown in Table 6-2.The registers within the CPU affected by reset are the Stack Pointer (SP), the Program Counter (PC), the IIR register, the EIR register, and the IP register. The IP register is set to all ones (disabling all interrupts), while all of the other listed CPU registers are reset to all zeros.

Table 6-2. Rabbit Internal I/O Registers

Register Name	Mnemonic	I/O Address	R/W	Reset
Global Control/Status Register	GCSR	0x00	R/W	11000000
Global Clock Modulator 0 Register	GCM0R	0x0A	W	00000000
Global Clock Modulator 1 Register	GCM1R	0x0B	W	00000000
Global Power Save Control Register	GPSCR	0x0D	W	0000x000
Global Output Control Register	GOCR	0x0E	W	00000000
Global Clock Double Register	GCDR	0x0F	W	00000000
MMU Instruction/Data Register	MMIDR	0x10	R/W	00000000
MMU Common Base Register	STACKSEG	0x11	R/W	00000000
MMU Bank Base Register	DATASEG	0x12	R/W	00000000
MMU Common Bank Area Register	SEGSIZE	0x13	R/W	11111111
Memory Bank 0 Control Register	MB0CR	0x14	W	00001000
Memory Bank 1 Control Register	MB1CR	0x15	W	xxxxxxxx
Memory Bank 2 Control Register	MB2CR	0x16	W	xxxxxxxx
Memory Bank 3 Control Register	MB3CR	0x17	W	xxxxxxxx
MMU Expanded Code Register	MECR	0x18	R/W	xxxxx000
Memory Timing Control Register	MTCR	0x19	W	xxxx0000
Breakpoint/Debug Control Register	BDCR	0x1C	W	0xxxxxxx
Slave Port Data 0 Register	SPD0R	0x20	R/W	xxxxxxxx
Slave Port Data 1 Register	SPD1R	0x21	R/W	xxxxxxxx
Slave Port Data 2 Register	SPD2R	0x22	R/W	xxxxxxxx
Slave Port Status Register	SPSR	0x23	R	00000000
Slave Port Control Register	SPCR	0x24	R/W	0xx00000
Global ROM Configuration Register	GROM	0x2C	R	0xx00000
Global RAM Configuration Register	GRAM	0x2D	R	0xx00000
Global CPU Configuration Register	GCPU	0x2E	R	0xx00001

User’s Manual 73