Jameco Electronics 2000, 3000 manual I/O Read Time Delays, I/O Write Time Delays

The following I/O read time delays were measured.

Table 16-5. I/O Read Time Delays

Time Delay	Output Capacitance
	30 pF	60 pF	90 pF
Max. clock to address delay (Tadr)	6 ns	8 ns	11 ns
Max. clock to memory chip select delay (TCSx)	6 ns	8 ns	11 ns
Max. clock to I/O chip select delay (TIOCSx)	6 ns	8 ns	11 ns
Max. clock to I/O read strobe delay (TIORD)	6 ns	8 ns	11 ns
Max. clock to I/O buffer enable delay (TBUFEN)	6 ns	8 ns	11 ns
Min. data setup time (Tsetup)		1 ns
Min. data hold time (Thold)		0 ns

The measurements were taken at the 50% points under the following conditions.

•T = -40°C to 85°C, V = 3.3 V

•Internal clock to nonloaded CLK pin delay ≤ 1 ns @ 85°C/3.0 V The following I/O write time delays were measured.

Table 16-6. I/O Write Time Delays

Time Delay	Output Capacitance
	30 pF	60 pF	90 pF
Max. clock to address delay (Tadr)	6 ns	8 ns	11 ns
Max. clock to memory chip select delay (TCSx)	6 ns	8 ns	11 ns
Max. clock to I/O chip select delay (TIOCSx)	6 ns	8 ns	11 ns
Max. clock to I/O write strobe delay (TIOWR)	6 ns	8 ns	11 ns
Max. clock to I/O buffer enable delay (TBUFEN)	6 ns	8 ns	11 ns
Max. high Z to data valid rel. to clock (TDHZV)	10 ns	12 ns	15 ns
Max. data valid to high Z rel. to clock (TDVHZ)	10 ns	12 ns	15 ns

The measurements were taken at the 50% points under the same conditions that the I/O read delays were measured.

I/O bus cycles have an automatic wait state and thus require 3 clocks plus any extra wait states specified.

See Table 16-2for delays at other voltages.

224 Rabbit 3000 Microprocessor