Jameco Electronics 3000, 2000 manual Short Chip Select Timing

B.1.12.2 Short Chip Select Timing

When short chip selects are enabled for read cycles, the chip select signals are active only for the last part of the bus cycle. Wait states are inserted between T1 and T2, so this will have no effect on the duration of the chip select signals in this mode. The timing diagrams below illustrate the actual timing for the different divided cases. In these cases the chip selects are two clock cycles (of the fast oscillator) long.

	T1	T2
oscillator
clock
ADDR	Valid
DATA
/CSx
/OEx

divide-by-8 mode

Figure B-3. Short Chip Select Timing: CLK/8, Read Operation

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