Jameco Electronics 2000, 3000 manual Memory Read Time Delays, Memory Write Time Delays

The following memory read time delays were measured.

Table 16-3. Memory Read Time Delays

Time Delay	Output Capacitance
	30 pF	60 pF	90 pF
Max. clock to address delay (Tadr)	6 ns	8 ns	11 ns
Max. clock to memory chip select delay (TCSx)	6 ns	8 ns	11 ns
Max. clock to memory read strobe delay (TOEx)	6 ns	8 ns	11 ns
Min. data setup time (Tsetup)		1 ns
Min. data hold time (Thold)		0 ns

The measurements were taken at the 50% points under the following conditions.

•T = -40°C to 85°C, V = 3.3 V

•Internal clock to nonloaded CLK pin delay ≤ 1 ns @ 85°C/3.0 V The following memory write time delays were measured.

Table 16-4. Memory Write Time Delays

Time Delay	Output Capacitance
	30 pF	60 pF	90 pF
Max. clock to address delay (Tadr)	6 ns	8 ns	11 ns
Max. clock to memory chip select delay (TCSx)	6 ns	8 ns	11 ns
Max. clock to memory write strobe delay (TWEx)	6 ns	8 ns	11 ns
Max. high Z to data valid rel. to clock (TDHZV)	10 ns	12 ns	15 ns
Max. data valid to high Z rel. to clock (TDVHZ)	10 ns	12 ns	15 ns

The measurements were taken at the 50% points under the same conditions that the mem- ory read delays were measured.

See Table 16-2for delays at other voltages.

218 Rabbit 3000 Microprocessor