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Jameco Electronics 2000, 3000 manual Use of Physical Memory Separate I & D Space Model

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	64k	64k+4*n		512k+4*n	512k+52k
0k	52k	alloc xcode		512k+4*n	1024k
0k	52k	xconsts	512k		1024k
			512k		alloc xdata vars
	Root
	I Space
		alloc consts		Variable	allocate vars
	Constant			Variable
	D Space			D Space
	Flash memory available			Ram memory available.
	for extended code, constant
	data.

Figure 8-6. Use of Physical Memory Separate I & D Space Model

In Figure 8-6arrows indicate the direction in which variables and constants are allocated as the compile or assemble proceeds. Each of these arrows starts at a constant location in physical memory. This is important because the Dynamic C debugging monitor needs to keep a small number of constants and variable in data space and it needs to be able to access these regardless of the state of the user program. The Dynamic C debugger vari- ables are kept at the top of the data segment starting at 52k and working down in memory. The user-program variables are allocated by the compiler starting just below the Dynamic C debugger data. The Dynamic C constants start at address zero. User constants are allo- cated stating at a low address just above the Dynamic C constants.

126	Rabbit 3000 Microprocessor

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Jameco Electronics 2000, 3000 manual Use of Physical Memory Separate I & D Space Model

Contents

Page Rabbit 3000 Microprocessor Rabbit Semiconductor TrademarksTable of Contents Rabbit Internal I/O Registers Parallel Ports 129 Rabbit 3000 Clocks 209 Appendix B. Rabbit 3000 Revisions 273 Rabbit 3000 Microprocessor Introduction Features and Specifications Rabbit User’s Manual 1shows a block diagram of the Rabbit CPU Summary of Rabbit 3000 Advantages Differences Rabbit 3000 vs. Rabbit Feature RabbitSerial ports with support for SDLC/HDLC IrDA Rabbit 3000 Design Features Rabbit 8-bit Processor vs. Other Processors Overview of On-Chip Peripherals and Features 1 5 V Tolerant InputsSerial Ports 4 32.768 kHz Oscillator Input System ClockCascaded Output Registers for Parallel Ports D and E Parallel I/ORabbit Slave PortAuxiliary I/O Bus TimersPWM Input Capture ChannelsPulse Width Modulation Outputs Quadrature Encoder InputsProgramming Port Separate Core and I/O Power PinsDesign Standards Spread Spectrum ClockDynamic C Support for the Rabbit Standard BiosRabbit 3000 Microprocessor Processor Registers Details on Rabbit Microprocessor FeaturesRabbit 3000 Microprocessor Addressing Memory Components Memory MappingExample of Memory Mapping Operation 4shows a memory interface unit Extended Code Space Use of XPC Segment Separate I and D Space Extending Data MemoryXpc window stack Using the Stack Segment for Data Storage Data RAM Root Code Practical Memory ConsiderationsUser’s Manual Instruction Set Outline Load or Store Data from or to a Constant Address Load Immediate Data to a RegisterOther 8-bit loads and stores are the following Load or Store Data Using an Index RegisterRegister Exchanges Register-to-Register Move7 16-bit Arithmetic and Logical Ops Push and Pop InstructionsBool SBC instruction can also be used to perform a sign extension Input/Output Instructions Manipulation of Boolean Variables How to Do It in Assembly Language-Tips and TricksZero HL in 4 Clocks Exchanges Not Directly ImplementedComparisons of Integers HLB Atomic Moves from Memory to I/O Space Interrupt Priority Interrupt StructureProcessor Priority Effect on Interrupts Effect of Processor Priorities on InterruptsPrivileged Instructions, Critical Sections and Semaphores Multiple External Interrupting DevicesCritical Sections Semaphores Using Bit B,HLComputed Long Calls and Jumps Precisely Timed Output Pulses Rabbit CapabilitiesPulse Width Modulation to Reduce Relay Power Open-Drain Outputs Used for Key Scan Using Open-Drain Outputs for Key ScanCold Boot Slave Port Slave Rabbit As a Protocol Uart PIN Assignments and Functions Pinout Lqfp PackageSame pin dimensions apply along the x axis and the y axis Mechanical Dimensions and Land PatternPC Board Land Pattern for Rabbit 3000 128-pin Lqfp Ball Grid Array Package C D E F G H J K L MNominal Ball Tolerance Ball Pitch Nominal Land Ball and Land Size DimensionsDesign Considerations All dimensions in mm Key Feature RecommendationBGA Package Outline Lqfp Tfbga Rabbit Pin DescriptionsRabbit Pin Descriptions Pin Pin Group Pin Name Direction Function NumbersVddcore Bus Timing Read and Write Bus TimingPins With Alternate Functions Description of Pins with Alternate FunctionsPF7 PWM3 AQD2A Parallel Port x Alternate Functions Control Bits Parallel Port x Alternate FunctionsSymbol Parameter Test Conditions Min Typ Max Units DC Characteristics3 Volt DC Characteristics Symbol Parameter Maximum RatingI/O Buffer Sourcing and Sinking Limit Rabbit 3000 Microprocessor Rabbit Internal I/O Registers On-Chip Peripheral ISR Starting Address Rabbit 3000 Peripherals and Interrupt Service VectorsDefault Values for all the Peripheral Control Registers Register Name Mnemonic Address ResetRabbit Internal I/O Registers Grev PEB7R PWM0R Tbcsr Sdar Processor Identification Global ROM Configuration RegisterGlobal RAM Configuration Register Miscellaneous FunctionsGcpu Rabbit Oscillators and ClocksGlobal CPU Register Global Revision RegisterRabbit Gcsr Global Control/Status RegisterClock Select Field of Gcsr Global Control/Status RegisterGcdr Recommended Delays Set In Gcdr for Clock DoublerClock Doubler Global Clock Double RegisterEffect of Clock Doubler User’s Manual Reduction in Peak Spectral Strength from Spectrum Spreader Clock Spectrum SpreaderChip Select Options for Low Power Address = 0x0D Global Power Save Control RegisterShort Chip Select Memory Read Global Output Control Register Gocr = 0x0E Output Pins CLK, STATUS, /WDTOUT, /BUFENTime/Date Clock Real-Time Clock 11. Real-Time Clock Control Register Rtccr adr = 10. Real-Time Clock RTCxR Data Registers12. Watchdog Timer Control Register Wdtcr adr = Watchdog Timer13. Watchdog Timer Test Register Wdttr adr = System Reset Pin Name Direction Reset Low Post-Reset† Recognized by CPU 14. Rabbit 3000 Reset Sequence and State of I/O PinsRabbit Interrupt Structure 15. Interrupts-Priority and Action to Clear Requests External Interrupt Line Logic External InterruptsInterrupt Vectors INT0 EIR,0x00/INT1 EIR,0x08 16. Control Registers for External InterruptsReg Name Reg Address Bits 7,6 Bits 5,4 Bits 3,2 Bits 1,0 Bootstrap Operation 102 Rabbit 3000 Microprocessor Pulse Width LSBs 1st 2nd 3rd 4th Pulse Width Modulator18. PWM MSB x Register 17. PWM LSB x RegisterInput Capture 106 Rabbit 3000 Microprocessor 19. Input Capture Control/Status Register Input Capture Control/Status RegisterIccsr ICT1R 20. Input Capture Control Register21. Input Capture Trigger x Register Iccr22. Input Capture Source x Register 23. Input Capture LSB x Register24. Input Capture MSB x Register Quadrature Decoder Rejected 25. Quadrature Decoder Control/Status Register Quad Decode Control/Status RegisterQdcsr QDC1R 26. Quadrature Decoder Control Register27. Quadrature Decoder Count Register Qdcr114 Rabbit 3000 Microprocessor Interface for Static Memory Chips Memory Interface and MappingRabbit Data Lines Static Address Lines Memory FlashRAM Memory Mapping Overview Memory-Mapping UnitProcessor Memory Mapping Unit Interface Memory Chips Segment Register Function 64KSegment Registers Segment Size RegisterMemory Interface Unit Memory Bank Control Register x MBxCR = 0x014 + Memory Bank Control RegistersMmidr Optional A16, A19 Inversions by Segment /CS1 EnableMMU Instruction/Data Register Mmidr = MMU Instruction/Data RegisterMemory Timing Control Register Memory Timing Control Register MTCR, adr =MMU Expanded Code Register MecrBdcr Allocation of Extended Code and DataBreakpoint/Debug Control Register BDCR, adr = 0x01C Breakpoint/Debug Control RegisterInstruction and Data Space Support RAM Use of Physical Memory Separate I & D Space Model How the Compiler Compiles to Memory 128 Rabbit 3000 Microprocessor Parallel Ports Parallel Port a Parallel Port a RegistersParallel Port a Data Register Bit Functions Parallel Port B Parallel Port B RegistersParallel Port B Register Bit Functions Parallel Port C Parallel Port C RegistersParallel Port C Register Bit Functions Parallel Port D Registers Parallel Port DPD7 Parallel Port D Register functions Parallel Port D Control Register adr =Bits 7 Bits 5 Bits 3 Bits 1 136 Rabbit 3000 Microprocessor PE0 Parallel Port E10. Parallel Port E Registers 12. Parallel Port E Control Register adr = 11. Parallel Port E Register functionsParallel Port F 13. Parallel Port F Registers14. Parallel Port F Register Functions 15. Parallel Port F Control Register adr = 0x03C Using Parallel Port a and Parallel Port FSummary Parallel Port a Parallel Port F Parallel Port G 16. Parallel Port G Registers17. Parallel Port G Data Register Functions Parallel Port G Control Register adr= 0x04C External I/O Timing with 1 wait state 10. I/O Bank Control RegistersWrite data Write strobe T1 Tw T2 Read data Read strobe Chip select strobeI/O Bank x Control Register Control Register Port E Address Pin A1513 Range External I/O Register Address Range and Pin Mapping148 Rabbit 3000 Microprocessor Timers Reload Register Operation Timer aTimer a I/O Registers Timer a I/O RegistersTimer a Capabilities Timer a Control and Status RegisterTacsr User’s Manual 153 Tapr Timer a Control RegisterTimer a Prescale Register TacrPractical Use of Timer a Timer B Timer B RegistersRegister Name Mnemonic Reset Address Tbcr Timer B Control and Status RegisterTimer B Control Register Tbcsr12. Timer B Count LSB Register Timer B Count MSB x Registers10. Timer B Count LSB x Registers 11. Timer B Count MSB RegisterUsing Timer B 160 Rabbit 3000 Microprocessor Serial Port Signals Serial Port Signal Name FunctionRabbit Serial Ports Clka User’s Manual 163 Serial Port Register Layout Signals Shown at Microprocessor Tx PinUser’s Manual 165 Serial Port C Registers Serial Port RegistersSerial Port a Registers Serial Port B RegistersSerial Port D Registers Serial Port E RegistersSerial Port F Registers Address Register All Ports Data Register All Ports10. Long Stop Register All Ports 11. Status Register Asynchronous Mode Only All Ports 12. Status Register Clocked Serial Ports A-D only Bits Value Description Clocked serial mode onlyBits Value Description Hdlc mode only 13. Status Register Hdlc Mode Ports E and F only14. Serial Port Control Register Ports a and B SacrSbcr Sdcr 15. Serial Port Control Register Ports C and DSccr Address = 0xE4Sfcr 16. Serial Port Control Register Ports E and FSecr Address = 0xCC17. Extended Register Asynchronous Mode All Ports 18. Extended Register Clocked Serial Mode Ports A-D only 19. Extended Register Hdlc Mode Ports E and F only Transmitter IRQ Serial Port InterruptTransmit Serial Data Timing Serial Port Synchronization Receive Serial Data TimingClocked Serial Ports Clock Polarities Supported in Clocked Serial ModeUser’s Manual 183 184 Rabbit 3000 Microprocessor Clocked Serial Timing Clocked Serial Timing With Internal ClockClocked Serial Timing with External Clock Valid Synchronous Communications on Ports E and F Last Byte Bit Pattern Valid Data Hits User’s Manual 189 190 Rabbit 3000 Microprocessor User’s Manual 191 Push AF IOI LD A,SCSR Serial Port Software SuggestionsTransmitting Dummy Characters Controlling an RS-485 Driver and ReceiverTransmitting and Detecting a Break Using a Serial Port to Generate a Periodic InterruptStop bit Parity, Extra Stop Bits with 7-Data-Bit CharactersParity, Extra Stop Bits with 8-Data-Bit Characters Stop bit Start bit Data bits 9th bit lowSupporting 9th Bit Communication Protocols Rabbit-Only Master/Slave ProtocolData Framing/Modbus User’s Manual 197 198 Rabbit 3000 Microprocessor SRD SCS Rabbit Slave PortSlave Port Read Cycle Following table explains the parameters used in Figure Symbol Parameter Minimum MaximumSlaveattn PB7 Typical Connection Slave Rabbit to Master Rabbit Register Mnemonic Internal Address External Address Hardware Design of Slave Port InterconnectionSlave Port Registers Slave Port RegistersBit Bits 6,5 Bit 3,2 Bits 1,0 Write Only Read Only Slave Port Control Register Spcr adr =Applications and Communications Protocols for Slaves Slave ApplicationsSlave Port Status Register Spsr adr = Master-Slave Messaging Protocol 208 Rabbit 3000 Microprocessor Rabbit 3000 Main Oscillator Circuit Rabbit 3000 ClocksLow-Power Design EMI Control Using the Clock Spectrum Spreader Power Supply Connections and Board LayoutGCM1R Spread Spectrum Enable/Disable RegisterSpread Spectrum Mode Select GCM0R214 Rabbit 3000 Microprocessor Memory Requirements at 3.3 V, -40C to +85C, Adr Bus 60 pF AC Timing SpecificationsMemory Access Time Access Enable Access MHzData and Clock Delays VDD ±10%, Temp, -40C-+85C maximum VDDNormal Strong 30 pF 60 pF 90 pF No dbl/dbl CSx Memory Read Time Delays Memory Write Time DelaysTime Delay Output Capacitance 30 pF 60 pF 90 pF CLK A190 CSx WEx D70 Example Clock Doubler Max-Min Clock Low Times 222 Rabbit 3000 Microprocessor Bufen 16.2 I/O Access TimeI/O Write Time Delays I/O Read Time DelaysFurther Discussion of Bus and Clock Timing Clock Doubler and Memory Timing Period Frequency Maximum Clock SpeedsMaximum Clock Speeds at 3.3 V Preliminary Conditions Commercial Ratings Industrial RatingsExternal Oscillator Buffer User’s Manual 229 Power and Current ConsumptionRabbit 3000 System Current vs. Frequency at 3.3 11. Sleepy Mode Current Consumption Current Consumption Mechanisms Sleepy Mode Current Consumption Memory Current Consumption Current is negligible for V 1.14 Battery-Backed Clock Current ConsumptionVoltage Current incl built-in buffer Reduced-Power External Main OscillatorRabbit Bios and Virtual Driver BiosBios Services Periodic Interrupt Bios AssumptionsWatchdog Timer Support Virtual DriverUser’s Manual 239 240 Rabbit 3000 Microprocessor Other Rabbit Software Power Management SupportUsing Assembly Language Using Library FunctionsReading and Writing I/O Registers Atomic Instruction Shadow RegistersUpdating Shadow Registers Interrupt While Updating RegistersTimer and Clock Usage Write-only Registers Without Shadow RegistersNon-atomic Instructions Format of the structure used is the following 246 Rabbit 3000 Microprocessor Summary Rabbit InstructionsFlag Description Spreadsheet ConventionsRabbit Z180 Meaning Symbols19.4 16-bit Indexed Loads and Stores Load Immediate DataLoad & Store to Immediate Address 19.3 8-bit Indexed Load and StoreRegister to Register Moves 19.5 16-bit Load and Store 20-bit AddressExchange Instructions Stack Manipulation Instructions19.9 16-bit Arithmetic and Logical Ops ADD A,HL 19.10 8-bit Arithmetic and Logical Ops19.12 8-bit Increment and Decrement 19.11 8-bit Bit Set, Reset and Test19.14 8-bit Shifts and Rotates 19.13 8-bit Fast a Register OperationsBlock Move Instructions Instruction PrefixesMiscellaneous Instructions Control Instructions Jumps and CallsFollowing instructions are privileged Privileged InstructionsDifferences Rabbit VS. Z80/Z180 Instructions Z80/Z180 Instructions Dropped Rabbit Instructions to Use Flag Register Key IOI and IOE I Column Symbol KeyRabbit Z180 Meaning Z V C EX AF,AF LD A,BC LDP HL,IX RRA 268 Rabbit 3000 Microprocessor Programming Port PIN Assignments Appendix A. the Rabbit Programming PortAlternate Programming Port Use of the Programming Port as a Diagnostic/Setup PortSuggested Rabbit Crystal Frequencies Non-Stock Crystals Appendix B. Rabbit 3000 Revisions 274 Rabbit 3000 Microprocessor User’s Manual 275 IL1T/IZ1T IL2T/IZ2T Discussion of Fixes and ImprovementsTable B-1. Summary of Rabbit 3000 Improvements and Fixes Rabbit Description 3000 3000ARabbit Internal I/O Registers Table B-2. Reset State of New Rabbit 3000A I/O RegistersIuer Rabbit Register Name Mnemonic 3000 3000A Address Reset On-Chip Peripheral Address Range ISR Starting Address Peripheral and ISR AddressUser’s Manual 281 Gcpu Grev Revision-Level ID RegisterTable B-5. Rabbit 3000 Revision Identification Information Processor Revision PackageSystem/User Mode Wpcr Memory ProtectionTable B-6. Write Protect Control Register Write Protect Control RegisterTable B-7. Write Protect Low Register Write Protect Low RegisterWplr Wpsar Table B-8. Write Protect High RegisterTable B-9. Write Protect Segment x Register WphrWpsblr Table B-10. Write Protect Segment x Low RegisterWrite Protect Segment x Low Register WpsalrWpsbhr Table B-11. Write Protect Segment x High RegisterWrite Protect Segment x High Register WpsahrFigure B-2. Simple Stack Protection Layout Stack ProtectionTable B-12. Stack Limit Control Register Table B-13. Stack Low Limit RegisterTable B-14. Stack High Limit Register Ramsr RAM Segment RelocationTable B-15. RAM Segment Register RAM Segment RegisterWdtcr Secondary Watchdog TimerTable B-16. Watchdog Timer Control Register-Updated Table B-17. Secondary Watchdog Timer RegisterNew UMA/UMS Opcodes New OpcodesTable B-18. New Rabbit 3000 Opcodes Instruction Bytes Clks OperationIOI/IOE Table B-19. Rabbit 3000 Revision Block Copy Opcode EffectsNew Block Copy Opcodes Source DestinationTable B-20. MMU Instruction/Data Register Expanded I/O Memory AddressingTable B-21 Bank x Control Register External I/O ImprovementsTable B-22. Global Power Save Control Register Short Chip Select Timing for WritesAddress = 0x000D Clock Select and Power Save Modes Table B-23. Global Control/Status RegisterTable B-24. Clock Select Field of Gcsr Figure B-3. Short Chip Select Timing CLK/8, Read Operation Short Chip Select TimingFigure B-4. Short Chip Select Timing CLK/6, Read Operation Figure B-6. Short Chip Select Timing CLK/2, Read Operation Figure B-7. Short Chip Select Timing 2 kHz, Read Operation Figure B-9. Short Chip Select Timing 8 kHz, Read Operation Figure B-11. Short Chip Select Timing 32 kHz, Read Operation Figure B-12. Short Chip Select Timing CLK/8, Write Operation Figure B-13. Short Chip Select Timing CLK/6, Write Operation Figure B-15. Short Chip Select Timing CLK/2, Write Operation Figure B-16. Short Chip Select Timing 2 kHz, Write Operation Figure B-18. Short Chip Select Timing 8 kHz, Write Operation 310 Rabbit 3000 Microprocessor Figure B-21. PWM Interrupt and Output Timing Pulse Width Modulator ImprovementsPWM LSB 1 Register Table B-25. PWM LSB 0 RegisterTable B-26. PWM LSB 1 Register PWM LSB 0 RegisterTable B-27. PWM LSB 2 and 3 Registers Address = 0x008CAddress = 0x008E QDC1HR Quadrature Decoder ImprovementsTable B-28. Quadrature Decoder Control Register Table B-29. Quadrature Decoder Count High RegisterUser’s Manual 315 Serial Ports E/F Pins with Alternate FunctionsAppendix C. SYSTEM/USER Mode System Mode User ModeTable C-1. Differences Between System and User Modes System/User Mode Opcodes Table C-2. New System/User Mode OpcodesInstruction Bytes Clk Operation Priv Table C-3. System/User Mode I/O Registers System/User Mode RegistersRegister Name Mnemonic Address Table C-4. I/O Addresses Inaccessible in User ModeInterrupts Figure C-1. Interrupt Handing in System/User ModePeripheral Interrupt Prioritization Table C-5. Interrupts-Priority and Action to Clear Requests Memory Protection Only Using the System/User ModeFigure C-3. System/User Mode Setup for Mixed Operation Mixed System/User Mode OperationComplete Operating System Figure C-4. System/User Mode Setup for Operating SystemTable D-1 Rabbit 3000A Internal I/O Registers Appendix D. Rabbit 3000A Internal I/O RegistersTable D-1. Rabbit 3000A Internal I/O Registers 0x03C0 00000000 Serial Port E User Enable Register 0x006A Xxxxxxxx Port D Bit 3 Register 0x0082 00000000 Bank 3 Control Register 0x0098 Xx000000 Interrupt 1 Control Register 0x00D1 Xxxxxxxx Serial Port B Long Stop Register 334 Rabbit 3000 Microprocessor User’s Manual 335 Page Numerics IndexMemory A16, A19 inversions /CS1 PWL2R, PWL3R 200