Jameco Electronics 2000, 3000 Multiple External Interrupting Devices, Ld Sp,Hl Ld Sp,Iy Ld Sp,Ix

3.5.2 Multiple External Interrupting Devices

The Rabbit 3000 has two distinct external interrupt request lines. If there are more than two external causes of interrupts, then these lines must be shared between multiple devices. The interrupt line is edge-sensitive, meaning that it requests an interrupt only when a rising or falling edge, whichever is specified in the setup registers, takes place. The state of the interrupt line(s) can always be read by reading Parallel Port E since they share pins with Parallel Port E.

If several lines are to share interrupts with the same port, the individual interrupt requests would normally be or’ed together so that any device can cause an interrupt. If several devices are requesting an interrupt at the same time, only one interrupt results because there will be only one transition of the interrupt request line. To resolve the situation and make sure that the separate interrupt routines for the different devices are called, a good method is to have a interrupt dispatcher in software that is aided by providing separate attention request lines for each device. The attention request lines are basically the inter- rupt request lines for the separate devices before they are or’ed together. The interrupt dis- patcher calls the interrupt routines for all devices requesting interrupts in priority order so that all interrupts are serviced.

3.5.3 Privileged Instructions, Critical Sections and Semaphores

Normally an interrupt happens at the end of the instruction currently executing. However, if the instruction executing is privileged, the interrupt cannot take place at the end of the instruction and is deferred until a non privileged instruction is executed, usually the next instruction. Privileged instructions are provided as a handy way of making a certain oper- ation atomic because there would be a software problem if an interrupt took place after the instruction. Turning off the interrupts explicitly may be too time consuming or not possi- ble because the purpose of the privileged instruction is to manipulate the interrupt con- trols. For additional information on privileged instructions, see Section 19.19, “Privileged Instructions”.

The privileged instructions to load the stack are listed below.

LD SP,HL

LD SP,IY

LD SP,IX

The following instructions to load SP are privileged because they are frequently followed by an instruction to change the stack segment register. If an interrupt occurs between these two instructions and the following instruction, the stack will be ill-defined.

LD SP,HL

IOI LD sseg,a

46 Rabbit 3000 Microprocessor