Jameco Electronics 3000, 2000 manual Differences Rabbit VS. Z80/Z180 Instructions

20.DIFFERENCES RABBIT VS. Z80/Z180

INSTRUCTIONS

The Rabbit is highly code compatible with the Z80 and Z180, and it is easy to port non I/O dependent code. The main areas of incompatibility are instructions that are concerned with I/O or particular hardware implementations. The more important instructions that were dropped from the Z80/Z180 are automatically simulated by an instruction sequence in the Dynamic C assembler. A few fairly useless instructions have been dropped and cannot be easily simulated. Code using these instructions should be rewritten.

The following Z80/Z180 instructions have been dropped and there are no exact substi- tutes.

DAA, HALT, DI, EI, IM 0, IM 1, IM 2, OUT, IN, OUT0, IN0, SLP, OUTI, IND, OUTD, INIR, OTIR, INDR, OTDR, TESTIO, MLT SP, RRD, RLD, CPI,

CPIR, CPD, CPDR

Most of these op codes deal with I/O devices and thus do not represent transportable code. The only opcodes that are not processor I/O related are MLT SP, DAA, RRD, RLD, CPI, CPIR, CPD, and CPDR. MLT SP is not a practical op code. The codes that are concerned with decimal arithmetic, DAA, RRD, and RLD, could be simulated, but the simulation is very inefficient. (The bit in the status register used for half carry is available and can be set and cleared using the PUSH AF and POP AF instructions to gain access.) Usually code that uses these instructions should be rewritten. The instructions CPI, CPIR, CPD, and CPDR are repeating compare instructions. These instructions are not very useful because the scan stops when equal compare is detected. Unequal compare would be more useful. They are difficult to simulate efficiently, so it is suggested that code using these instructions be rewritten, which in most cases should be quite easy.

The following op codes are dropped.

RST 0, RST 8, RST 0x30

The remaining RST instructions are kept, but the interrupt vector is relocated to a variable location the base of which is established by the EIR register. RST can be simulated by a call instruction, but this is not done automatically by the assembler since most of these instructions are used for debugging by Dynamic C.

The following instruction has had its op code changed.

EX (SP),HL - old opcode 0x0E3, new opcode - 0x0ED-0x054

User’s Manual 259