Chapter3 HardwareOverview
ATE Series User Manual 3-2 ni.com

Figure 3-2 showsthe blo ck diagram for the AT-MIO-64E-3.

Figure3-2. AT-MIO-64E-3Block Diagram

Timing
PFI/ Trigger
I/O Connector
3
RTSIBusAT I/O Channel
DigitalI/O (8)
12-Bit
Sampling
A/D
Converter
EEPROM
Configuration
Memory
+
NI-PGIA
Gain
Amplifier
Calibration
Mux
MuxMode
Selection
Switches
Analog
Muxes
Voltage
REF
Calibration
DACs
Dither
Circuitry
Trigger
Analog
Trigger
Circuitry
2
TriggerLevel
DACs
6
Calibration
DACs
DAC0
DAC1
3
DAQ- STC
AnalogInput
Timing/Control
AnalogOutput
Timing/Control
DigitalI/O
Trigger
Counter/
TimingI/O
RTSIBus
Interface
DMA/
Interrupt
Request
Bus
Interface
(32)
(32)
DAC
FIFO
8
Data(16)
AIControl
Data(16)
Analog
Input
Control
EEPROM
Control
DMA
Interface
DAQ-PnP
DAQ-STC
Bus
Interface
Plug
and
Play
Analog
Output
Control
8255
DIO
Control
Bus
Interface
IRQDMA
Data
Transceivers
AOControl
ADC
FIFO