Chapter4 ConnectingSignals
©NationalInstruments Corporation 4-39 ATE Series User Manual
The ADC switchesto hold mode within 60 ns of the selected edge. This
hold-mode delay time is a function of temperature and does not vary from
oneconversion to the next. Separate the CONVERT* pulses by at least one
conversionperiod.
Thesample interval counter on the AT E Series device normally generates
theCONVERT* signal unless you select some external source. The counter
is started bythe STARTSCAN signal and continues to count down and
reloaditself until the scan is finished. It then reloads itself in readiness for
the nextSTARTSCAN pulse.
A/D conversionsgenerated by either an internal or external CONVERT*
signalare inhibited unless theyoccur wit hin a DAQsequence. Scans
occurring within a DAQsequence may be gated by either the hardware
(AIGATE)signal or software command register gate.
AIGATESignal
Any PFIpin can ext ernally input the AIGATE signal, which is not
availableas an output on the I/O connector. The AIGATE sig nalcan mask
offscans in a DAQ sequence. You can configure the PFI pin you select as
the sourcefor t he AIGATE signal in thelevel-detection mode. You can
configure the polarity selection for the PFI pin for either active high or
active low. In the level-detection mode if AIGATE is active, the
STARTSCAN signal is masked off and no scans can occur.
The AIGATEsignal can neither stop a scan in progress nor continue a
previouslygated-off scan; in other words, once a scan has started, AIGATE
does not gate offconversions until the beginning of the next scan and,
conversely,if conversionsare bein g gatedo ff,AIGATE does not gate them
back on until the beginning of the nextscan.
SISOURCE Signal
Any PFIpin can externally input the SISOU RCEsignal, w hich isnot
available as an output on the I/O connector. The onboard scan interval
counteruses the SISOURCE signal asa clock to time the generation of the
STARTSCAN signal. You must configure the PFI pin you select as the
sourcefor the SISOU RCE signal in the level-detection mode. You can
configure the polarity selection for the PFI pin for either active high or
active low.
Themaximum allowed frequency is 20 MHz, with a minimum pulse width
of 23 ns high or low.There is no minimum frequency limitation.