
Chapter4 ConnectingSignals
ATE Series User Manual 4-50 ni.com
Ifan internal timebase clock is used, the gate signal cannot be synchronized
withthe clock. In this case, gates applied close to a source edge take effect
either on that source edge or on the next one. This arrangement results in
an uncertainty of one source clock period with respect to unsynchronized
gatingsources.
The OUT output timing parameters arereferenced to the signal at the
SOURCE input or to one of the internally generated clock signals on
the ATE Series devices. Figure 4-37 shows the OUT signal referenced to
the rising edge of a source signal. Any OUT signal state changes occur
within 80 ns after the rising or falling edge of the source signal.
FREQ_OUT SignalThis signal is available only as an output on the FREQ_OUT pin. The
FREQ_OUT signal is the output of the AT E Series device frequency
generator.The frequen cyg enerator is a 4-bit counter that can divide its
inputclock by the numbers 1 through 16. The input clock of the frequency
generator is softwaresel ectable from the internal 10 MHz and 100 kHz
timebases. The output polarity is software selectable. This output is set to
high-impedance at startup.
Timing Specifications for Digital I/O Ports A, B, and C♦AT-MIO-16DE-10only
Inaddition to its function as a digitalI/O port, digital port C , PC<0..7>, can
alsobe used for handshaking when performing data tran sfers with ports A
and B.The signals assigned to port C depend on the mode in which it is
programmed.In mode 0, port C is considered two 4-bit I/O ports. In modes
1and 2, port C is used for status and handshaking signals with two or three
additionalI/O bit s. Table4-7 summarizes the signal assignment s of port C
foreach programmable mode. Refer to Table 4-7 for descriptions of the
signals for port C.
Table4-7. Port C Signal Assignments
Programming
Mode
GroupA GroupB
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Mode0 I/O I/O I/O I/O I/O I/O I/O I/O
Mode1 Input I/O I/O IBFASTBA*INTRASTBB*IBFBBINTRB
Mode1 Output OBFA*ACKA*I/O I/O INTRAACKB*OBFB*INTRB