Chapter4 ConnectingSignals
©NationalInstruments Corporation 4-49 ATE Series User Manual
leave the DIO7pi n freefor gene raluse. Fig ure 4-37 shows the timing
requirementsfor the GATE and SOURCE input signals and the timing
specifications for the OUT output signals of the AT E Series device.
Figure4-37. GPCTR Timing Summary
TheGATE and OUT signal transitions shownin Figure 4-37are referenced
tothe rising edge of the SOURCE signal. This timing diagram assumes that
the counters are programmed to count rising edges. The same timing
diagram,but with the source signal inverted and referenced to the falling
edgeof the source signal, would apply w hen the counter is programmed to
countfalling edges.
The GATEinput timing parameters are referenced to the signal at the
SOURCE input or to one of the internally generated signals on the
ATE Series device. Figure 4-37 shows the GATEsignal referenced to
the rising edge of a source signal. The gatemu st bevalid (either high or
low)for at least 10 ns before the rising or falling edge of a source signal
forthe gate to take effect at that source edge, as shown by tgsu and tgh in
Figure 4-37. The gate signal is not required to be held after the activeedge
ofthe source signal.
tsc
tsc tsp tsp
tsp
VIH
VIL
VIH
VIL
VOH
VOL
tgsu
tgsu tgh
tgh
tgw
tgw
tout
tout
SourceClock Period
SourcePulse Width
GateSetup Time
GateHold Time
GatePulse Width
OutputDelay Time
50ns minimum
23ns minimum
10ns minimum
0ns minimum
10ns minimum
80ns maximum
SOURCE
GATE
OUT