Table 5–1. P–Series EVFU Codes – PI Line Enabled

 

ASCII

 

 

 

 

 

Data Bits

 

 

 

Channel

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Hex

Dec

Code

PI

8

7

6

5

4

3

2

1

 

 

00

0

NUL

1

X

X

X

0

0

0

0

0

1

(TOF)

01

1

SOH

1

X

X

X

0

0

0

0

1

2

 

02

2

STX

1

X

X

X

0

0

0

1

0

3

 

03

3

ETX

1

X

X

X

0

0

0

1

1

4

 

04

4

EOT

1

X

X

X

0

0

1

0

0

5

 

05

5

ENQ

1

X

X

X

0

0

1

0

1

6

 

06

6

ACK

1

X

X

X

0

0

1

1

0

7

 

07

7

BEL

1

X

X

X

0

0

1

1

1

8

 

08

8

BS

1

X

X

X 0 1 0 0 0

9

 

09

9

HT

1

X

X

X 0 1 0 0 1

10

 

0A

10

LF

1

X

X

X 0 1 0 1 0

11

 

0B

11

VT

1

X

X

X

0

1

0

1

1

12

(VT)

0C

12

FF

1

X

X

X 0 1 1 0 0

13

 

0D

13

CR

1

X

X

X

0

1

1

0

1

14

 

0E

14

SO

1

X

0

0

0

1

1

1

0

15

 

0F

15

SI

1

X

0

0

0

1

1

1

1

16

 

6E

110

n

1

X

1

1

0

1

1

1

0

Start Load

6F

111

o

1

X

1

1

0

1

1

1

1

End Load

X = Undefined, 0 or 1

 

 

 

1 = High

 

 

 

 

0 = Low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE: Disabling or enabling the PI interface line is configuration controlled.

5–4

Vertical Format Units

Page 78
Image 78
Printronix P3000 Series manual P-Series Evfu Codes PI Line Enabled, Data Bits Channel Hex Dec Code