Texas Instruments MSP50C6xx manual Reduced Power Modes

Reduced Power Modes

overall power consumption during that state. The various subsystems that determine (or are affected by) the depth of sleep include the:

Processor core, which is driven by the CPU clock

PLL clock circuitry

PLL reference oscillator

C6xx periphery, which is driven by the master clock

-TIMER1 and TIMER2 PDM pulsing

The deepest sleep achievable on the C6xx, for example, is a mode where all of the previously listed subsytems are stopped. In this state, the device draws less than 10 ∝ A of current and obtains the greatest power savings. It may be awakened from this state using an external interrupt (input port).

A number of control parameters determine which of the internal components are left running after the IDLE instruction. In most cases, the states of these controls may be mixed in any combination. There are three combinations, however, which are primarily useful. The three modes (light, mid, and deep sleep) are executed through the independent control of two bits: 1) the idle state clock control, and 2) the reference oscillator enable. The other pertinent controls simply enhance the performance of the modes dictated by these two. Table 2–3 gives a listing of all of the controls which should be maintained by the programmer before engaging the IDLE instruction. In some cases, it will be impossible to wake from sleep unless certain controls are set appropriately before going to sleep. (In those cases, only the hardware RESET low-to-high will bring the device back into its normal operating state.)

The top row in Table 2–3 lists the first of the two primary controls, namely, the idle state clock control. The idle state clock control determines the status of the master clock (MC) during sleep. Setting the idle state control causes the CPU clock, the PLL clock circuitry, and the MC to stop after the next IDLE instruction. Clearing the idle state control causes only the CPU clock to stop after IDLE. The PLL clock circuitry governs the MC and determines its rate. Whenever the PLL circuitry is suspended, therefore, the MC stops. The idle state clock control is accessed at bit 10 in the ClkSpdCtrl register (refer to Section 2.8.3, Clock Speed Control Register, for more information).

The reference oscillator enable is the other control which selects between the three reduced power modes listed in Table 2–3. This control may be one of two bits, depending on which oscillator reference is implemented in circuitry (refer to Section 2.8.3, Clock Speed Control Register). When using the resistor-trimmed oscillator (RTO), the reference oscillator enable appears as bit 8 in the ClkSpdCtrl register. When using the crystal-referenced oscillator (CRO), the reference oscillator enable appears as bit 9 in the ClkSpdCtrl register. If both bits 8 and 9 are clear, then no reference oscillator is enabled.

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