Texas Instruments manual MSP50C6xx Core Processor Block Diagram, MSP50C6xx Architecture

Figure 2–1. MSP50C6xx Core Processor Block Diagram

Interrupt Inputs

				Peripheral
		Interrupt Flag Register (IFR)†		Interface
Multiplier (MR)†	Shift Value (SV)†	Control Register (CTRL)†
		Interrupt Processor
17 x 17 Multiplier		Serial Interface Register†		Serial
				Interface
	Product High (PH)†	Oscillator Register†
		Timer Period (PRD1 and PRD2)†
				VCO
	MUX	Timer Register (TIM1 and TIM2)†
				Frequency
16 bit ALU				Divider
				Instruction
		AP0–AP3†		Decoder
		Accumulator Pointer
32 Accumulators (AC0–AC31)†			+1
Column Exchange		Incrementor
		Top Of Stack (TOS)†
	Stack (R7)	Program Counter (PC)†
	Page (R6)	Protection Register (PR)†
	Index (R5)	Data Pointer (DP)†
	Loop (R4)
	R3
	R2
	R1	MUX
	R0
	MUX	String Register†
				Test Code
		MUX		2k x 17 bit
Arithmetic Unit				Program Memory
		Repeat Counter†
				30k x 17 bit
		Status Register (STAT)†		Macro Calls
MUX		Flag Register†		Vectors
	Data Memory
	640 x 17 bit

† Indicates internal programmable registers.

MSP50C6xx Architecture 2-3