Timer Registers | Texas Instruments MSP50C6xx manual

Timer Registers

This software-controlled trim for the RTO is not a replacement for the external reference-resistor mounted at pins OSCIN and OSCOUT. Also, note that this adjustment has no effect on the rate of the CRO reference oscillator.

2.9 Timer Registers

The C6xx contains two identical timers, TIMER1 and TIMER2. Each includes a period register and a count-down register. The period register (PRD1 or PRD2) defines the initial value for the counter, and the count-down register (TIM1 or TIM2) does the counting. When the count-down register decrements to the value 0x0000, then the value currently stored in the period register is loaded to the count-down register. The count-down register then resumes counting again from that value.

For each TIMER, there is an interrupt-trigger event associated with the TIMER’s underflow condition (the point of reaching 0x0000 and then re-setting again). When enabled, the interrupt INT1 is triggered by the underflow of TIMER1, and the interrupt INT2 is triggered by the underflow of TIMER2. INT1 and INT2 are the second and third-highest priority interrupts in the C6xx. Refer to Section 2.7, Interrupt Logic, for a summary of the interrupt logic, and to Section 2.6.3, Interrupt Vectors, for a listing of the interrupt vectors.

Both the period and the count-down registers are readable and writeable as port-addressed registers:

(16-bit wide location)

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

00

PRD1 register†

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

address 0x3A

TIMER1 Period

TIM1 register†

T

T

T

T

T

T

T

T

T

T

T

T

T

T

T

T

address 0x3B

TIMER1 Count-Down

Triggers INT1 on underflow

PRD2 register

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

address 0x3E

TIMER2 Period

TIM2 register

T

T

T

T

T

T

T

T

T

T

T

T

T

T

T

T

address 0x3F

TIMER2 Count-Down

Triggers INT2 on underflow

P : period register (initial counter value)

T : count-down register (counts from the value in P) 0x0000 : default state of both registers after RESET LOW

†TIMER1 may be associated with the comparator function, if the comparator enable bit is set. Refer to Section 3.3, Comparator, for details.

MSP50C6xx Architecture

2-31

Image 55

Texas Instruments MSP50C6xx manual Timer Registers

Contents

MSP50C6xx Mixed-Signal Processor User’s Guide Important Notice Iii How to Use This ManualAbout This Manual Notational Conventions Csr -a /user/ti/simuboard/utilities Here is a sample program listingNotational Conventions Information About Cautions and Warnings Information About Cautions and WarningsTrademarks This book may contain cautions and warningsPage Contents Contents Assembly Language InstructionsPeripheral Functions Code Development Tools Contentsix Customer Information Applications PLL Performance -27 2-10 Instruction Execution and Timing Contentsxi Tables Tables Contentsxiii Xiv Introduction to the MSP50C6xx Features of the MSP50C6xx Features of the MSP50C6xx Aids for the Handicapped ApplicationsConsumer Education Industrial Development Device MSP50P614 Development Device MSP50P614 Functional Description for the MSP50C614 Functional Description for the MSP50C614 Functional Description for the MSP50C614 Resistor Trim Oscillator Connections Crystal Reference Oscillator Connections Reset Circuit MSP50C601, MSP50C604, and MSP50C605 MSP50C601, MSP50C604, and MSP50C605Page MSP50C6xx Architecture Architecture Overview MSP50C6xx Architecture MSP50C6xx Core Processor Block Diagram Computational Unit Block Diagram Computation Unit Computation UnitMultiplier Signed and Unsigned Integer Representation Computation Unit Arithmetic Logic Unit Overview of the Multiplier Unit Operation Accumulator Block Overview of the Arithmetic Logic Unit Points to AC Register #Points to Offset Data Memory Address Unit Data Memory Address Unit Data Memory Address Unit RAM Configuration Data Memory Addressing Modes Bit Logic Unit Program Counter UnitProgram Counter Unit Memory Map Memory Organization RAM and ROMMemory Organization RAM and ROM Peripheral Communications Ports C6xx Memory Map not drawn to scale Summary of MSP50C614’s Peripheral Communications Ports Reset LOW Interrupt Vectors Summary of C614’s Peripheral Communications PortsInterrupt Name ROM address Event Source Interrupt Priority ROM Code Security True Protection Marker N TM Block Protection WordAddress 0x7FFE Write only = the value programmed at FM5 … FM0 false = the value programmed at TM5 … TM0 trueProtection marker ≡ the binary complement of N TM Macro Call Vectors Interrupt LogicInterrupt Logic IFR Bit wide location 00 ← INT number Interrupt Logic Interrupt Initialization Sequence Clock Control Clock ControlOscillator Options PLL Performance PLL Performance Clock frequency kHz = Pllm register value + 1 ⋅ 65.536 kHz Clock Speed Control Register ClkSpdCtrl register RTO Oscillator Trim Adjustment ClkSpdCtrl Value Copied Shaded Rtrim Register Read Only Applies to MSP50C6xx Device Only Timer Registers Timer Registers Timer Registers Reduced Power Modes Reduced Power Modes Reduced Power Modes Reduced Power Modes Programmable Bits Needed to Control Reduced Power Modes Component Determined Deeper sleep … relatively less power →By Controls Event Determined Deeper sleep … Global interrupt enable is SET Execution Timing Execution Timing Peripheral Functions MSP50C604 MSP50C605 I/OGeneral-Purpose I/O Ports MSP50C614 0x14h 0x1Ch 0x24h Possible control values = High-Z Input Control register address 0x04h†Peripheral Functions Dedicated Input Port F Input Port F Dedicated Output Port GData register address Totem-Pole Output Port G Branch on D Port Internal and External Interrupts Summary of the interrupts is given in Table InterruptsInterrupt Vector Source Trigger Event Priority Comment Digital-to-Analog Converter DAC Digital-to-Analog Converter DACPulse-Density Modulation Rate DAC Control and Data Registers Overflow bits Least-significant data value Ignored bits PDM Clock Divider PDM Clock Divider Digital-to-Analog Converter DAC DAC Example 3-1 -kHz Sampling Rate Example 3-2 -kHz Sampling Rate Comparator INT6 INT7 TIMER1 Enable Comparator Address Bit wide location Low Interrupt/General Control RegisterInterrupt/General Control Register IntGenCtrl register Interrupt/General Control Register Hardware Initialization States Hardware Initialization States Hardware Initialization States Bit Bit Name Initialized Value Description Instruction Set Summary Assembly Language Instructions System Registers Introduction Postdecrement Assembly Language InstructionsTop of Stack, TOS System Registers Product Low Register PL Product High Register PHAccumulators AC0-AC31 Bits 16 Accumulator Pointers AP0-AP3Indirect Register R0-R7 Bit Status Register Stat String Register STR Function Status Register Stat 1 MSP50P614/MSP50C614 Instruction Syntax Instruction Syntax and Addressing Modes Next a Addressing Mode EncodingAddressing Modes Bit Opcode Rx Bit Description Addressing Mode Bits and adrs Field Description Auto Increment and Auto Decrement Modes MSP50P614/MSP50C614 Addressing Modes Summary Clocks Words Addressing Operation, † Syntax Flag addressing mode encoding, flagadrsFlag Repeat Flagadrs ADD AP0, 0x1A Immediate AddressingSyntax Example Memory Operand Direct AddressingMOV *0x012F * 2, *A0 Mulr *0x02A1 Rx x = 0 Address Memory Operand ++  --  ++R5 Indirect AddressingIndirect Addressing Syntax SyntaxOperation Movb *R7++, A3 Relative AddressingMOV A2, *R0 *R4++ Rx x = 0 Address Index Register R5 Operand A0, *R3+R5R6 page register Address Bit positive offset Operand Rx x = 0 Address Memory Operand MOV A3, *R6+0x10 XOR TF1, *R6+0x20 Flag AddressingTF1, *0x20 Or TF2, *R6+0x02 8 Tag/Flag Bits TF1,*ram1 TF1 bit in Stat is set!? Possible sources of confusion Consider the following code Instruction Classification 10. Symbols and ExplanationSymbol Explanation Instruction Classification Class Sub- Description 11. Symbols and Explanation11. Instruction Classification Next a Accumulator control bits as described in Table Class Sub Description Class 1 Instructions Memory and Accumulator Reference 12. Classes and Opcode Definition C1b 13. Class 1 Instruction Encoding14. Class 1a Instruction Description C1a ~A~ C1b Mnemonic Description 15. Class 1b Instruction Description Class 2 Instructions Accumulator and Constant Reference 17. Class 2a Instruction Description 16. Class 2 Instruction EncodingC2a Mnemonic Description ADD An ~, An ~, imm16 , next a 18. Class 2b Instruction DescriptionClass 3 Instruction Accumulator Reference C2b Mnemonic Description Subs An~, An~, An Modified ADD An~, An~, An , next a 19. Class 3 Instruction Encoding20. Class 3 Instruction Description Mnemonic Description Carry status CF Zero or be set equal to the sign bit Xsgm dependentSUB a n~, a n~, PH , next a ALU status is modified. String bit causes subtract with From the offset accumulator A~=1 or accumulator PH msbs extended by XM mode bit. Transfer the lowerMOV SV, An~ , next a Is modified 21. Class 4a Instruction Encoding Class 4 Instructions Address Register and Memory Reference 25. Class 4d Instruction Description 22. Class 4a Instruction Description23. Class 4b Instruction Description 24. Class 4c Instruction Description Adrs. Transfer status is modified Class 5 Instructions Memory Reference26. Class 5 Instruction Encoding 27. Class 5 Instruction Description Tag bit Dressing mode adrs. Transfer status is modifiedMOV adrs, TOS Stag adrs C6a Mnemonic Description Class 6 Instructions Port and Memory Reference28. Class 6a Instruction Encoding 29. Class 6a Instruction Description Class 7 Instructions Program Control 30. Class 6b Instruction DescriptionC6b Mnemonic Description Ccc 31. Class 7 Instruction Encoding and DescriptionVector8 Jcc 32. Class 8a Instruction Encoding Class 8 Instructions Logic and Bit C8a Mnemonic Description 33. Class 8a Instruction Description34. Class 8b Instruction Description Class 9 Instructions Miscellaneous C9a Mnemonic Description 35. Class 9a Instruction Encoding36. Class 9a Instruction Description 37. Class 9b Instruction Description C9c Mnemonic Description Bit, Byte, Word and String Addressing38. Class 9c Instruction Description 39. Class 9d Instruction Description 0000h MS Byte LS Byte Global Flags Relative0000h 0001h 0002h 0040h 0041h Nnnn 17th Bit Word MOV A0, *0x0004 Mode Address Used Data Order Rx Post modify †40. Data Memory Address and Data Relationship Movb A0, *0x0003 Which uses the absolute word memory address Rflag MSP50P614/MSP50C614 Computational Modes MSP50P614/MSP50C614 Computational Modes 41. MSP50P614/MSP50C614 Computational Modes Computational Setting Resetting Function Mode Instruction SXM Example 4.6.2 Sovm Example 4.6.1 SovmExample 4.6.1 SXM Hardware Loop Instructions Hardware Loop Instructions Syntax Operation Limitations 42. Hardware Loops in MSP50P614/MSP50C614Completion of the BEGLOOP/ENDLOOP block Program memory *address = data String Instructions43. Initial Processor State for String Instructions Data memory *address = data Mulapl A0, A0~ Instructions Description Data Transfer Lookup Instructions44. Lookup Instructions Lookup Instructions MOV An, adrs SUB An MOV An, *An Xk-2 Xk+2 Xk-1 xk+1 32 or Input/Output InstructionsSpecial Filter Instructions Input/Output Instructions Special Filter Instructions Special Filter Instructions STR,0 Go back N words to wrap around 0x0100 0x01020x0104 0x0106 After FIR/COR execution Important Note About Setting the Stat Register Firkcoeffs Coeffarray Coeffarray address FIRK/CORK only Program memory FIRK/CORKCoeffarray Samplebuf address FIR/COR only = 0..N Samplebuf Coeffarray is stored Conditionals Conditionals Port4 ≤ Port6 ≤ Symbol MeaningOperands Offset16 ≤ Flg AdrsnClk Dma n Pma n Offset nPort n 45. Auto Increment and Decrement 46. Addressing Mode Bits and adrs Field Description47. Flag Addressing Syntax and BIts Individual Instruction Descriptions Individual Instruction Descriptions Execution 14.1 ADD Add word See Also Description PC PC + Flags Affected AddbOpcode Clock , clk Words , w Adds Add String Adds A1, A1~, A1 14.4 Bitwise A3, *R4 ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XorsTF2, *0x0020 Clock , clk Word , w Andb Bitwise and ByteSrc byte PC PC + OF, SF, ZF, CF are set accordingly Ands A0, A0~, A0 Ands Bitwise and StringAnds A0, A0~, *R2 Order to loop N times Begloop Begin LoopSave next instruction address PC + Flags Affected None Opcode Call Unconditional Subroutine Call RET TOS 14.9 CccNOP True condition Not true condition 48. Names for cc Syntax Alternate Syntax Description Crnbe CALL, VCALL, RET, Iret0x2010 CTF1 CMPB, CMPS, Jcc, Ccc 14.10 CMP Compare Two WordsStat flags set by src src1 operation PC = PC + w CMP R0, R5 CMP R2, 0xfe20 Cmpb R3 Cmpb Compare Two Bytes Cmps A2, A2~ Cmps Compare Two StringsPC PC + w Flags Affected Cmps A1~ Rxeven = Rxeven + R5 With RPT instruction. See .11 for more detail on the setup14.13 COR Correlation Filter Function An, *Rx 3nR+2 Xeven = R xeven + R5 Cork Correlation Filter FunctionSample data. During Cork execution, interrupt is queued 3n R+2 BEGLOOP, Inte Endloop End LoopDecrement R4 by n 1 or PC first address after Begloop else Argument, it assumes n =1 Dest , mod Extsgn Sign Extend Word~ , next a Copy accumulator sign flag SF to all 16 bits of a n ~ An~ Extsgns Sign Extend String 100 Rxeven++ Assembly Language Instructions 10114.18 FIR FIR Filter Function Coefficients in RAM An, *Rx 2nR+2 102 Firk Assembly Language Instructions 103 104 Idle Halt Processor INS, OUT, Outs 14.21 Input From Port Into WordA2~, 0x3d IN, OUT, Outs 14.22 INS Input From Port Into String IM is Stat bit PC PC + Flags Affected None Opcode Intd Interrupt DisableAssembly Language Instructions 107 STAT.IM Clock, clk Word, w With RPT, clk Class Interrupt EnableInte INTD, Iret Iret Return From Interrupt Assembly Language Instructions 109 RCF and RZF affected by post-modification of R Conditional Jumps Cc names Assembly Language Instructions 111 If test condition is false, a NOP is executed Jtag 0x2010, R2++ See Also JMP, CALL, C cc ExampleJNZ JE 0x2010, R3++R5 Instruction Operation 14.27 JMP Unconditional JumpPost-modify R x if specified See Also Cc, CALL, C cc Example 14.28 MOV Move Data Word From Source to Destination STR, imm8 XSF, XZF are set accordinglyClock , clk Word , w With RPT , clk Class TF n, cc , R MOV adrs, DP Assembly Language Instructions 117 With some operand types Example 4.14.28.12 MOV *0x0200 * 2, R0 MOVU, MOVT, MOVB, MOVBS, MovsExample 4.14.28.10 MOV MR, A3, --A Example 4.14.28.11 MOV A1~, *A1 Example 4.14.28.18 MOV *R6 + 8 * 2, DP Example 4.14.28.13 MOV R1, 0x0200Example 4.14.28.15 MOV *0x0200 * 2, R0 Transfer R5 to R0 Example Execution An + PH Movaph Move With Adding PHMOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs MOVAPH, MOVTPH, MOVTPHS, MOVSPH, Movsphs Movaphs Move With Adding PHExecution + PH Background. See .8 for more details Copy data memory byte pointed by R2 to accumulator A0 Movb Move Byte From Source to DestinationCopy value of unsigned src byte to dest byte Movb A0, *R2 Movb A0, 0xf2 Movb *R2, A0Movb R2 Movbs *0x0200, A2 Movbs Move Byte String from Source to DestinationTAG bit is set to bit 17th value Movbs A2, *0x0200 Adrs , *An Movs Move String from Source to DestinationAn ~ , adrs Adrs , An ~ Movs A1~, A1 MOVU, MOV, MOVT, MOVB, MovbsMovs A2~ Movs A1, A1~ MOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs Movsph128 Details An second word PH MR contents of adrsAssembly Language Instructions 129 Movsphs Move String With Subtract From PH MOVU, MOV, MOVT, MOVB, MOVBS, Movs MovtPC PC + w Flags Affected None Opcode Available Copy the value pointed by R3 to MR Movu Move Data UnsignedTAG bit is set accordingly UM is set to MOV, MOVB, MOVT, MOVBS, Movs Xxxxxx Xxxx00 Flag Bit MR/SV An S APn132 MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, Mulapl 14.38 MUL Multiply RoundedMR * src PC PC + w Flags Affected Accumulator pointer if specified Mulapl Mulr Multiply Rounded With No Data TransferMR * src PC PC + Flags Affected MULS, MUL, MULAPL, MULSPL, MULSPLS, MULTPL, Multpls PH,PL MR * src string Length nS+2, where nS is the value in STR registerAssembly Language Instructions 135 Muls Multiply String With No Data Transfer MULAPLS, MULSPL, MULSPLS, MULTPL, Multpls Mulapl Multiply and Accumulate ResultPH ,PL MR * src Background. See .8 for more detail MR * src Mulapls Multiply String and Accumulate ResultMULAPL, MULSPL, MULSPLS, MULTPL, Multpls Syntax Description Mulspl adrs Mulspl Multiply and Subtract PL From AccumulatorOccuring in the background. See .8 for more details MULSPLS, MULTPL, MULTPLS, MULAPL, Mulapls Syntax Description Mulspls adrs Mulspls Multiply String and Subtract PL From AccumulatorFrom dest string MULSPL, MULTPL, MULTPLS, MULAPL, Mulapls Multiply MR by data memory word, move PL to a n Multpl Multiply and Transfer PL to Accumulator~ , a n ~ , next a Value of src. The 16 MSBs Example 4.14.46.2 Multpls A2, A2~ MultplsExecution PH, PL MR * src PC PC + Flags Affected MULTPL, MULAPL, MULAPLS, MULSPL, Mulspls Example 4.14.47.1 Negac A3~, A3, --A Negac Two’s Complement Negation of AccumulatorAccumulator NEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs Assembly Language Instructions 143Negacs Two’s Complement Negation of Accumulator String Dest accumulator string Execution PC PC + 14.49 NOP No OperationRPT Example 4.14.50.1 Notac A3~, A3, --A Notac One’s Complement Negation of AccumulatorNOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, Xors NEGAC, Negacs A3~ Notacs One’s Complement Negation of Accumulator StringAccumulator string Negacs TFn bits in Stat register are set accordingly 14.52 or Bitwise Logical orAccumulator pointers are allowed with some operand types 148 ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NotacsOr A0, *R0++R5 Or TF1, *R6+0x22 OR, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs 14.53 ORB Bitwise or ByteOr src Accumulator is affected ORS A0, A0~, A0 14.54 ORS Bitwise or StringPC + w Flags Affected OR, ORB, AND, ANDS, XOR, XORS, NOTAC, Notacs Address is multipled by 4 to get the actual port address 14.55 OUTOUTS, IN, INS Port6 , An ~ Outs Output String to PortPort6 specified in the instruction OUT, IN, INS CALL, i.e., RET followed by a RET should not be allowed 14.57 RET Return From Subroutine CALL, CccPC TOS R7 R7 Flags Affected Sflag , Stag , Rtag Rflag Reset Memory FlagExample 4.14.58.2 Rflag *R6 + STAT.FM Reset Fractional Mode SyntaxResets the fractional mode. Clears FM bit of Stat 14.59 RFM Stat .OM Rovm Reset Overflow ModeSaturation output normal mode Resets the overflow mode to zero After execution completes 14.61 RPT Repeat Next InstructionIf RPT adrs8 Load src to repeat counter Load imm8 to repeat counter Rtag *R6+0x0003 Rtag Reset TagStag , Rflag , Sflag Rtag *R6+0x0002 SXM 14.63 RXM Reset Extended Sign ModeAssembly Language Instructions 159 STAT.XM 160 Address flagadrs only accesses the 17 th bitSflag Set Memory Flag Rflag , Stag , Rtag Set fractional mode. Set FM bit of Stat to 14.65 SFM Set Fractional ModeMode for signed fractional arithmetic Assembly Language Instructions 161 Shls 14.66 SHL Shift LeftPH , PL Accumulator. Use Shlac for this purpose Example 4.14.67.2 Shlac A1~, A1, --A Shlac Shift Left AccumulatorIts offset. LSB of result is set to zero Shift accumulator A1 by one bit to the left Accumulators in the string Shlacs Shift Left Accumulator String Individually164 Example 4.14.69.3 Shlapl A1, A1, ++A Shlapl Shift Left with AccumulateExample 4.14.69.1 Shlapl A0, *R4++R5 Shlapl A2, *R1++ Shift data memory string left, add PL to a n Shlapls Shift Left String With AccumulateShift a n ~ string left, addb PL to a n ~ An~ Assembly Language Instructions 167Shls Shift Left Accumulator String to Product Execution PH, PL Example 4.14.72.3 Shlspl A1, A1, ++A Shlspl Shift Left With Subtract PLExample 4.14.72.1 Shlspl A0, *R4++R5 Shlspl A2, *R1++ Shift RAM string left, subtract PL from An Assembly Language Instructions 169Shlspls Shift Left String With Subtract PL NS+3 NR+3 Example 4.14.74.3 Shltpl A1, A1, ++A Shltpl Shift Left and Transfer PL to AccumulatorExample 4.14.74.1 Shltpl A0, *R4++R5 Shltpl A2, *R1++ Shift the accumulator string A1 by nSV bits to the left Shltpls Shift Left String and Transfer PL to AccumulatorReceives the same data as PH SHLTPL, SHLAPL, SHLAPLS, SHLSPL, Shlspls Example 4.14.76.2 Shrac A1~, A1, ++A Shrac Shift Accumulator RightRegister Shift right one bit the accumulator A1 Shltpls Assembly Language Instructions 173Shracs Shift Accumulator String Right SHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, Shltpl STAT.OM Set Overflow Mode SyntaxOutput DSP mode Sovm RTAG, RFLAG, Sflag StagStag *0x401 An ~ , An ~ , imm16 , next a 14.80 SUB SubtractDest, src , src1 , next a An ~ , An , adrs , next a SUB R3, R5 Example 4.14.80.2 SUB A0, A0, 2, ++ASUB A1, A1~, A1 SUB A3~, A3, *R4 Syntax Description Subb a n, imm8 Subb Subtract ByteSubtract 0x45 from accumulator A2 byte Subtract 0xF2 from register R3 byte Subs Subtract Accumulataor String Assembly Language Instructions 179NR+2 180 Subs A2, A2, A2~Subs A2, A2~, A2 Subs A3~, A3~, PH RXM 14.83 SXM Set Extended Sign ModeSets extended sign mode status register Stat bit 0 to Assembly Language Instructions 181 See Also RET, IRET, CALL, C cc Example Vcall Vectored CallPush PC + 0x7F00 R7 R7 + Flags Affected TAG bit is set accordingly Src is flagadrs 14.85 XOR Logical XORXOR src For two operands XOR src For three operands Example 4.14.85.1 XOR A1, A1, 0x13FF XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NotacsExample 4.14.85.2 XOR A0, A0, 2, ++A Xorb Logical XOR Byte Assembly Language Instructions 185XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Xors A2, A2~, A2 Xors Logical XOR StringDest string XOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs ZAC A1~, ++A 14.88 ZAC Zero AccumulatorPC PC + Flags Affected ZF = Zacs ZAC Reset the content of offset accumulator string A1~ to zeroZacs Zero Accumulator String Zero the specified accumulator string Instruction Set Encoding Assembly Language Instructions 189Instruction Set Encoding 190 Assembly Language Instructions 191 192 Assembly Language Instructions 193 194 Assembly Language Instructions 195 196 Description True condition Not true condition Assembly Language Instructions 197 Instruction Set Summary An, An~ Pma16 , Rmod Assembly Language Instructions 199An~, An~ , next a An~, pma16 MR , imm16 , next a Adrs, a n~ , next a~, adrs , next a An ~, imm16 , next a Flagadrs† , TFn Assembly Language Instructions 201Adrs, TOS STR, adrs Adrs An ~, An ~, imm16 , next a ~, a n~, a n , next a ~ , next a~, a n~ , next a ~ , a n~ An~, An~, An An~, An~ , next a NR+3 Assembly Language Instructions 203TFn, flagadrs NR+3 TFn, cc , Rx An~, An~, pma16 ~, a n~, PH ~, a n~~, a n, a n~ , next a ~, a n, a n~ Conditional on ZF=0 and SF=1 Not condition ZF≠ Or SF≠ Conditional on RCF=1 Not condition RCF=0Conditional on RZF=0 and RCF=1 Not condition RZF≠ 0 or RCF≠ Conditional on RZF=1 Not condition RZF=0 Instruction Set Summay 206Assembly Language Instructions MC = Pllm value+1 ⋅ 131.07 kHz 208Assembly Language Instructions 209 Language InstructionsSummay Instruction Set Summay 210Assembly Language Instructions Code Development Tools Introduction Code Development Tools Pin IDC Connector top view looking at the board MSP50C6xx Development Tools Guidelines MSP50C6xx Development Tools GuidelinesCategories of MSP50Cxx Development Tools SDK50P614 kit of 15 MSP50P614s SPEECH-EVM†PC50C604† Tools Definitions MSP50C6xx Development Tools Guidelines Software Tools-Definitions Documentation MSP50C6xx Code Development ToolsSystem Requirements Hardware Tools Setup Green Target board power Red MSPSCANPORTI/F power Yellow Assembler AssemblerAssembler Directives Examples #ELSE see #IF and #IFDEF An assembly language program #ENDIF #IF expression Do something here#ELSE Do other things here #IFNDEF symbol Example #IFDEF symbol Assembler Foreword CompilerCompiler External References Variable TypesType Name Mnemonic Range Size in Bytes Example With Arguments Defines a replacement string for a given stringDirectives Without Arguments See #if directive Include Files #define STRLENGTHi Major Differences between C and C Initialization values are stored in program memory Function Prototypes and DeclarationsInitializations RAM Usage String Functions String FunctionsOperator can take the following values predefined constants An example of the use of xferconst is Constant Functions Signed comparison of a and b. a is in A0, b is in A0~ Implementation DetailsComparisons This section is C- specific Ugt Assembly VectorUnsigned comparison of a and b. a is in A0, b is in A0~ Ult Low Address High Address DivisionFunction Calls Stack frame has the following structure On RET Programming ExampleCmmfunc bidonint i1,char *i2 is valid, but On Call #include cmmmacr.h Reserved Programming Example, C -- With Assembly Routines Implementation Details R7Param Addb R7,2 To C function return in roncoreturn OldR5 Return Addr Param R7,R5 Stack data Param R7,R5 Stack data Before call Parameter Return Addr Param Stack data To ASM function return EfficiencyEfficiency Efficiency Example 5-1. First Project Real Time Clock Example Jrtc.rpj Hmodules MAINRAM.IRX Allocated by changing Efficiency CMM1.ASM Allocated as follows Sixth file, cmm1ram.asm, allocates memory for cmm1.asm MAIN.CMM Example 5-2. Second Project C-- With Speech Isr Tim2isr.asm dacisr.asm J tim1isr.asm Celp Celp.irxUtil.obj Dspvar.irx dsputil.asm getbits.asm speak.asm speak.irx Dsp Tens.qfmMelp Ampm.qfm Ramendcustomer Ramstartcustomer New C-- callable functions were declared global Assembly routines that will be called are declared externalClock will need to say Cmmfunc speakHours Example 5-3. Third Project C-- with an LCD Lcd Lcd.asm Lcd.irx Melp.irx Melp.objCelp Ampm.qfm Days.qfm Ones.qfm Teens.qfm External lcdsetio external lcdinit Case Efficiency Beware of Stack Corruption Beware of Stack Corruption Reported Bugs With Code Development Tool Reported Bugs With Code Development Tool Applications Application Circuits Application Circuits Applications6-3 ∝ F 22 pFMSP50P614 only 100 kΩ 3300 pF Initializing the MSP50C6xx Initializing the MSP50C6xx Applications6-5 File init.asm JNZ Itsacpart Itsappart Applications6-7 Getting Started TI-TALKS Example CodeTI-TALKS Example Code Applications6-9 RAM OverlayCreating a New Project RAM Overlay Adding Customer Variables RAM Overlay Common Problems Page Customer Information Die Bond-Out Coordinates Mechanical InformationPackage Information Customer Information Signal and Pad Descriptions for the MSP50C614 Signal and Pad Descriptions for the MSP50C605 Signal and Pad Descriptions for the MSP50C601 Signal and Pad Descriptions for the MSP50C604 Pin QFP Mechanical Information 13 NOM Extra pin 3 4 5 6 7 8 9 10 11 12 13 Bottom View 13 12 11 10 9 8 7 6 5 4 3 2 Bottom view Bottom View of 120-Pin PGA Package of the MSP50P614 Customer Information Fields in the ROM Customer Information Fields in the ROM0x0006 Device number 0x0614 Software Design Hardware Design Speech SpecificationSpeech Development Cycle Device Production Sequence Device Production Sequence Code Letter PJM Loopin 100-Pin QFP Ordering InformationNew Product Release Forms Nprf 6xx New Product Release Forms Nprf Approval of Prototypes and Authorization to Start Production NEW Product Release Form for MSP50C604 Option Selection New Product Release Forms Nprf NEW Product Release Form for MSP50C605 Option Selection New Product Release Forms Nprf NEW Product Release Form for MSP50C601 Option Selection New Product Release Forms Nprf Topic Additional Information Additional Information Additional Information